公开(公告)号：US20130043451A1

公开(公告)日：2013-02-21

申请号：US13431612

申请日：2012-03-27

Applicant: Seung-ryul Lee ,  Young-bae Kim ,  Chang-jung Kim ,  Myoung-jae Lee ,  Ji-hyun Hur ,  Dong-soo Lee ,  Man Chang ,  Chang-bum Lee ,  Kyung-min Kim

Inventor： Seung-ryul Lee ,  Young-bae Kim ,  Chang-jung Kim ,  Myoung-jae Lee ,  Ji-hyun Hur ,  Dong-soo Lee ,  Man Chang ,  Chang-bum Lee ,  Kyung-min Kim

IPC: H01L45/00

CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/12 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/55 ,  G11C2213/71 ,  G11C2213/72

Abstract: Nonvolatile memory elements and memory devices including the nonvolatile memory elements. A nonvolatile memory element may include a memory layer between two electrodes, and the memory layer may have a multi-layer structure. The memory layer may include a base layer and an ionic species exchange layer and may have a resistance change characteristic due to movement of ionic species between the base layer and the ionic species exchange layer. The ionic species exchange layer may have a multi-layer structure including at least two layers. The nonvolatile memory element may have a multi-bit memory characteristic due to the ionic species exchange layer having the multi-layer structure. The base layer may be an oxygen supplying layer, and the ionic species exchange layer may be an oxygen exchange layer.

Abstract translation: 包括非易失性存储元件的非易失性存储元件和存储器件。 非易失性存储元件可以包括两个电极之间的存储层，并且存储层可以具有多层结构。 记忆层可以包括基层和离子物种交换层，并且由于离子物质在基层和离子物质交换层之间的移动而具有电阻变化特性。 离子物种交换层可以具有包括至少两层的多层结构。 由于具有多层结构的离子物质交换层，非易失性存储元件可能具有多位存储特性。 基底层可以是供氧层，离子物种交换层可以是氧交换层。

公开(公告)号：US08351436B2

公开(公告)日：2013-01-08

申请号：US12597850

申请日：2008-08-19

Applicant: Bin-yeong Yoon ,  Man-soo Han ,  Sung-chang Kim ,  Hark Yoo ,  Dong-soo Lee ,  Jong-deog Kim ,  Kyeong-hwan Doo ,  Yong-tae Kim ,  Kwang-ok Kim ,  Bong-kyu Kim ,  Geun-yong Kim ,  Sung-hoon Kwak ,  Mun-seob Lee ,  Le Quan

Inventor： Bin-yeong Yoon ,  Man-soo Han ,  Sung-chang Kim ,  Hark Yoo ,  Dong-soo Lee ,  Jong-deog Kim ,  Kyeong-hwan Doo ,  Yong-tae Kim ,  Kwang-ok Kim ,  Bong-kyu Kim ,  Geun-yong Kim ,  Sung-hoon Kwak ,  Mun-seob Lee ,  Le Quan

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04J3/1694 ,  H04J2203/0067 ,  H04Q11/0067 ,  H04Q2011/0064

Abstract: Provided are an apparatus and method for efficiently and dynamically allocating a bandwidth on a Time Division Multiple Access-based Passive Optical Network (TDMA PON). The dynamic bandwidth allocation apparatus for uplink data transmission of a plurality of Optical Network Units (ONUs) including a plurality of class queues corresponding to Transmission Container (T-CONT) types, the plurality of ONUs connected to an Optical Line Terminal (OLT) on a Passive Optical Network (PON), includes: a class queue information storage unit storing information regarding a bandwidth allocation period and an allocatable bandwidth amount for each T-CONT type; an allocation check table unit checking the bandwidth allocation period for the T-CONT type received from the class queue information storage unit, and determining an allocatable bandwidth amount for the T-CONT type; and a bandwidth allocation unit allocating an uplink bandwidth to the T-CONT type with reference to the bandwidth allocation period and the allocatable bandwidth amount for the T-CONT type, and re-allocating to each ONU an uplink bandwidth remaining after allocating a total uplink bandwidths to all T-CONT types.

Abstract translation: 提供了一种用于在基于时分多址接入的无源光网络（TDMA PON）上有效且动态地分配带宽的装置和方法。 用于包括对应于传输容器（T-CONT）类型的多个类队列的多个光网络单元（ONU）的上行链路数据传输的动态带宽分配装置，连接到光线路终端（OLT）上的多个ONU 无源光网络（PON）包括：类队列信息存储单元，存储关于每个T-CONT类型的带宽分配周期和可分配带宽量的信息; 分配检查表单元，检查从类队列信息存储单元接收到的T-CONT类型的带宽分配周期，以及确定T-CONT类型的可分配带宽量; 以及带宽分配单元，参照带宽分配期间和T-CONT类型的可分配带宽量向T-CONT类型分配上行链路带宽，并且在分配总上行链路之后向每个ONU重新分配剩余的上行链路带宽 所有T-CONT类型的带宽。

公开(公告)号：US08278640B2

公开(公告)日：2012-10-02

申请号：US12805783

申请日：2010-08-19

Applicant: Dong-soo Lee ,  Chang-bum Lee ,  Chang-jung Kim

Inventor： Dong-soo Lee ,  Chang-bum Lee ,  Chang-jung Kim

IPC: H01L29/02

CPC classification number: G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A resistive random access memory (RRAM) devices and resistive random access memory (RRAM) arrays are provided, the RRAM devices include a first electrode layer, a variable resistance material layer formed of an oxide of a metallic material having a plurality of oxidation states, an intermediate electrode layer on the variable resistance material layer and formed of a conductive material having a lower reactivity with oxygen than the metallic material, and a second electrode layer on the intermediate electrode layer. The RRAM arrays include at least one of the aforementioned RRAM devices.

Abstract translation: 提供了电阻随机存取存储器（RRAM）器件和电阻随机存取存储器（RRAM）阵列，RRAM器件包括第一电极层，由具有多个氧化态的金属材料的氧化物形成的可变电阻材料层， 所述可变电阻材料层上的中间电极层由与所述金属材料相比氧的反应性低的导电材料和所述中间电极层上的第二电极层形成。 RRAM阵列包括至少一个上述RRAM设备。

公开(公告)号：US20120032132A1

公开(公告)日：2012-02-09

申请号：US13204138

申请日：2011-08-05

Applicant: Seung-ryul Lee ,  Chang-jung Kim ,  Young-bae Kim ,  Myoung-jae Lee ,  Ji-hyun Hur ,  Dong-soo Lee ,  Man Chang ,  Chang-bum Lee

Inventor： Seung-ryul Lee ,  Chang-jung Kim ,  Young-bae Kim ,  Myoung-jae Lee ,  Ji-hyun Hur ,  Dong-soo Lee ,  Man Chang ,  Chang-bum Lee

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/146

Abstract: Nonvolatile memory elements may include a first electrode, a second electrode, a first buffer layer, a second buffer layer and a memory layer. The memory layer may be between the first and second electrodes. The first butter layer may be between the memory layer and the first electrode. The second buffer layer may be between the memory layer and the second electrode. The memory layer may be a multi-layer structure including a first material layer and a second material layer. The first material layer may include a first metal oxide which is of the same group as, or a different group from, a second metal oxide included in the second material layer.

Abstract translation: 非易失性存储元件可以包括第一电极，第二电极，第一缓冲层，第二缓冲层和存储层。 存储层可以在第一和第二电极之间。 第一黄油层可以在存储层和第一电极之间。 第二缓冲层可以在存储层和第二电极之间。 存储层可以是包括第一材料层和第二材料层的多层结构。 第一材料层可以包括与包括在第二材料层中的第二金属氧化物相同的基团或与其不同的基团的第一金属氧化物。

公开(公告)号：US20100260498A1

公开(公告)日：2010-10-14

申请号：US12747330

申请日：2009-04-28

Applicant: Kwang-ok Kim ,  Yong-tae Kim ,  Dong-soo Lee

Inventor： Kwang-ok Kim ,  Yong-tae Kim ,  Dong-soo Lee

IPC: H04J14/00

CPC classification number: H04J3/1694 ,  H04Q11/0067 ,  H04Q2011/0064

Abstract: A gigabit passive optical network (GPON) system for fiber to the home (FTTH) service must provide a down-stream data rate of an optical band to provide IPTV service with hundreds of channels to subscribers, and must be able to provide an upstream data rate of an optical band using a currently available BM-IC chip. A currently available BM-IC chip for a GPON has 1.244 Gbps and 2.488 Gbps modes. Accordingly, an optical network terminal (ONT) for a GPON that is capable of providing a downstream transmission band of 10-Gbps and an upstream transmission band of 1.244 Gbps or 2.488 Gbps, and a method for processing an upstream frame in the terminal, are provided. The GPON ONT can provide 20 Mbps, high-definition IPTV service with 500 channels and can provide both upstream data rates of 1.244 Gbps and 2.488 Gbps according to a user's selection without using an additional device.

Abstract translation: 用于光纤到家庭（FTTH）业务的千兆无源光网络（GPON）系统必须提供光带的下行数据速率，以向用户提供数百个信道的IPTV服务，并且必须能够提供上行数据 使用当前可用的BM-IC芯片的光学带宽率。 目前用于GPON的BM-IC芯片具有1.244 Gbps和2.488 Gbps模式。 因此，能够提供10Gbps的下行传输频带和1.244Gbps或2.488Gbps的上行传输频带的GPON的光网络终端（ONT）以及用于处理终端中的上行帧的方法是 提供。 GPON ONT可以提供具有500个通道的20 Mbps高清晰度IPTV服务，并可根据用户的选择提供1.244 Gbps和2.488 Gbps的上行数据速率，而无需使用其他设备。

公开(公告)号：US20070215977A1

公开(公告)日：2007-09-20

申请号：US11654003

申请日：2007-01-17

Applicant: Myoung-jae Lee ,  Yoon-dong Park ,  Hyun-sang Hwang ,  Dong-soo Lee

Inventor： Myoung-jae Lee ,  Yoon-dong Park ,  Hyun-sang Hwang ,  Dong-soo Lee

IPC: H01L29/00 ,  G11C11/00

CPC classification number: H01L45/12 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/56 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: Provided is a resistance random access memory (RRAM) device and a method of manufacturing the same. A resistance random access memory (RRAM) device may include a lower electrode, a first oxide layer on the lower electrode and storing information using two resistance states, a current control layer made of a second oxide on the first oxide layer and an upper electrode on the current control layer.

Abstract translation: 提供一种电阻随机存取存储器（RRAM）装置及其制造方法。 电阻随机存取存储器（RRAM）器件可以包括下电极，下电极上的第一氧化物层和使用两个电阻状态存储信息，在第一氧化物层上由第二氧化物制成的电流控制层， 当前控制层。

公开(公告)号：US20070079187A1

公开(公告)日：2007-04-05

申请号：US11518981

申请日：2006-09-12

Applicant: Sun Choi ,  Dong-soo Lee ,  Yong-kyun Sun ,  Hyun-ho Kim

Inventor： Sun Choi ,  Dong-soo Lee ,  Yong-kyun Sun ,  Hyun-ho Kim

IPC: G11C29/00

CPC classification number: G11C29/56 ,  G01R31/2808 ,  G11C5/04 ,  G11C29/56016

Abstract: A system for testing memory modules having a rotating-type board mounting portion with a plurality of mounting surfaces positioned at different planes and connected around an axis to form a rotatable structure, at least one circuit board mounted on each mounting surface, an input/output portion, a rotational motor coupled to a rotational shaft for rotating the rotatable structure, and a central controller electrically connected to the circuit boards.

Abstract translation: 一种用于测试具有旋转型板安装部分的存储器模块的系统，其具有位于不同平面上的多个安装表面并且围绕轴线连接以形成可旋转结构，安装在每个安装表面上的至少一个电路板，输入/输出 耦合到用于旋转可旋转结构的旋转轴的旋转电机，以及电连接到电路板的中央控制器。

公开(公告)号：US09786761B2

公开(公告)日：2017-10-10

申请号：US14955205

申请日：2015-12-01

Applicant: Dong-soo Lee ,  Hu-yong Lee ,  Won-keun Chung ,  Hoon-joo Na ,  Taek-soo Jeon ,  Sang-jin Hyun

Inventor： Dong-soo Lee ,  Hu-yong Lee ,  Won-keun Chung ,  Hoon-joo Na ,  Taek-soo Jeon ,  Sang-jin Hyun

IPC: B82Y10/00 ,  H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06

CPC classification number: H01L29/512 ,  B82Y10/00 ,  H01L21/28185 ,  H01L21/823456 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit device includes a substrate including an active region, an interfacial layer including a lower insulating layer on the active region, the lower insulating layer doped with a chalcogen element having an atomic weight equal to or greater than 16, a gate insulation layer on the interfacial layer, and a gate electrode on the gate insulation layer.

公开(公告)号：US08947905B2

公开(公告)日：2015-02-03

申请号：US13523429

申请日：2012-06-14

Applicant: Man Chang ,  Young-bae Kim ,  Dong-soo Lee ,  Chang-bum Lee ,  Seung-ryul Lee ,  Chang-jung Kim ,  Myoung-jae Lee ,  Kyung-min Kim

Inventor： Man Chang ,  Young-bae Kim ,  Dong-soo Lee ,  Chang-bum Lee ,  Seung-ryul Lee ,  Chang-jung Kim ,  Myoung-jae Lee ,  Kyung-min Kim

IPC: G11C11/00 ,  G11C11/56 ,  G11C13/00

CPC classification number: G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069

Abstract: A method of driving a nonvolatile memory device including applying a reset voltage to a unit memory cell, reading a reset current of the unit memory cell, confirming whether the reset current is within a first current range, if the reset current is not within the first current range, changing the reset voltage and applying a changed reset voltage or applying again the reset voltage to the unit memory cell after applying a set voltage to the unit memory cell, if the reset current is within the first current range, confirming whether a difference between the present reset current and an immediately previous set current is within a second current range, and, if the difference is not within the second current range, applying the reset voltage or applying again the reset voltage to the unit memory cell after applying a set voltage to the unit memory cell.

Abstract translation: 一种驱动非易失性存储器件的方法，包括：将复位电压施加到单元存储单元，读取单元存储单元的复位电流，确认复位电流是否在第一电流范围内，如果复位电流不在第一电流范围内 电流范围，如果复位电流在第一电流范围内，则改变复位电压并施加改变的复位电压或再次将施加设定电压的复位电压施加到单元存储单元， 在当前复位电流和紧接在前的设定电流之间的电流在第二电流范围内，并且如果该差值不在第二电流范围内，则在应用组合之后施加复位电压或再次施加复位电压到单元存储单元 电压到单元存储单元。

公开(公告)号：US08772750B2

公开(公告)日：2014-07-08

申请号：US13115549

申请日：2011-05-25

Applicant: Chang-bum Lee ,  Chang-jung Kim ,  Young-bae Kim ,  Myoung-jae Lee ,  Ji-hyun Hur ,  Dong-soo Lee ,  Man Chang ,  Seung-ryul Lee

Inventor： Chang-bum Lee ,  Chang-jung Kim ,  Young-bae Kim ,  Myoung-jae Lee ,  Ji-hyun Hur ,  Dong-soo Lee ,  Man Chang ,  Seung-ryul Lee

IPC: H01L47/00 ,  H01L29/06

CPC classification number: H01L27/2409 ,  G11C13/0007 ,  G11C2213/51 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/72 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A non-volatile memory element includes: a memory layer disposed between a first electrode and a second electrode; and a buffer layer disposed between the memory layer and the first electrode. The memory layer includes a first material layer and a second material layer. The first material layer and the second material layer are configured to exchange ionic species to change a resistance state of the memory layer.

Abstract translation: 非易失性存储元件包括：设置在第一电极和第二电极之间的存储层; 以及设置在所述存储层和所述第一电极之间的缓冲层。 存储层包括第一材料层和第二材料层。 第一材料层和第二材料层被配置为交换离子物质以改变存储层的电阻状态。