公开(公告)号：US20050176198A1

公开(公告)日：2005-08-11

申请号：US10775163

申请日：2004-02-11

申请人： Stephan Kudelka

发明人： Stephan Kudelka

IPC分类号： C25F3/12 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/82 ,  H01L21/8242

CPC分类号： H01L27/1087 ,  C25F3/12 ,  H01L21/3063

摘要： A method of forming trench capacitors in, e.g., a DRAM device, using an electrochemical etch with built-in etch stop to fabricate well-defined bottle-shaped capacitors is described. The process includes formation of a sacrificial silicon layer after initial deep trench formation, wherein the sacrificial layer is formed by doping, and upon its removal, a bottle trench is formed. A second region of doped silicon located below the sacrificial layer is resistant to the chemical etch performed to remove the sacrificial layer, and thereby renders the bottle trench formation process self-limiting.

摘要翻译： 描述了在例如DRAM器件中形成沟槽电容器的方法，其中使用具有内置蚀刻停止件的电化学蚀刻来制造明确定义的瓶形电容器。 该过程包括在初始深沟槽形成之后形成牺牲硅层，其中牺牲层通过掺杂形成，并且在其去除时形成瓶沟槽。 位于牺牲层下方的掺杂硅的第二区域对于去除牺牲层而进行的化学蚀刻是耐受的，从而使瓶形成沟槽形成过程是自限制的。

公开(公告)号：US06740595B2

公开(公告)日：2004-05-25

申请号：US10122996

申请日：2002-04-12

申请人： Stephan Kudelka ,  Helmut Tews ,  Alexander Michaelis ,  Uwe Schroeder ,  Martin Popp ,  Kristin Schupke ,  Daniel Koehler

发明人： Stephan Kudelka ,  Helmut Tews ,  Alexander Michaelis ,  Uwe Schroeder ,  Martin Popp ,  Kristin Schupke ,  Daniel Koehler

IPC分类号： H01L21311

CPC分类号： H01L27/1087 ,  H01L21/30604 ,  H01L27/10829 ,  H01L29/66181

摘要： A method for eching a recess in a polysilicon region of a semiconductor device by applying a solution of NH4OH in water to the polysilicon.

摘要翻译： 一种通过将NH 4 OH溶液施加到多晶硅中来捕获半导体器件的多晶硅区域中的凹陷的方法。

公开(公告)号：US06555430B1

公开(公告)日：2003-04-29

申请号：US09723420

申请日：2000-11-28

申请人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

发明人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/964

摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

摘要翻译： 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

公开(公告)号：US06437401B1

公开(公告)日：2002-08-20

申请号：US09824957

申请日：2001-04-03

申请人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

发明人： Jack A. Mandelman ,  Stephan Kudelka ,  Andreas Knorr ,  Stephen Rahn ,  Helmut Tews ,  Michael Wise

IPC分类号： H01L2976

CPC分类号： H01L27/1087 ,  H01L27/10861 ,  H01L27/10864 ,  H01L29/945

摘要： A trench capacitor structure for improved charge retention and method of manufacturing thereof are provided. A trench is formed in a p-type conductivity semiconductor substrate. An isolation collar is located in an upper portion of the trench. The substrate adjacent the upper portion of the trench contains a first n+ type conductivity region and a second n+ type conductivity region. These regions each abut a wall of the trench and are separated vertically by a portion of the p-type conductivity semiconductor substrate. A void which encircles the perimeter of the trench is formed into the wall of the trench and is located in the substrate between the first and second n+ type conductivity regions.

摘要翻译： 提供了用于改善电荷保留的沟槽电容器结构及其制造方法。 在p型导电性半导体衬底中形成沟槽。 隔离套环位于沟槽的上部。 与沟槽上部相邻的衬底包含第一n +型导电区​​和第二n +型导电区​​。 这些区域各自邻接沟槽的壁并且被p型导电性半导体衬底的一部分垂直分开。 围绕沟槽的周边的空隙形成沟槽的壁，并且位于第一和第二n +型导电区​​域之间的衬底中。

公开(公告)号：US06426253B1

公开(公告)日：2002-07-30

申请号：US09576465

申请日：2000-05-23

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L21/76237 ,  H01L21/823487 ,  H01L27/10841 ,  H01L27/10867

摘要： A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

摘要翻译： 使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。 电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。 低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。 然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。 然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或在沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分 沟槽暴露进一步加工。 或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。 自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

公开(公告)号：US06335247B1

公开(公告)日：2002-01-01

申请号：US09597389

申请日：2000-06-19

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

IPC分类号： H01L21336

CPC分类号： H01L27/10864 ,  H01L27/10876

摘要： A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

摘要翻译： 一种使用选择性湿蚀刻在集成电路中形成垂直取向器件的方法，以仅去除深沟槽中的一部分侧壁，以及由此形成的器件。 虽然沟槽周边的一部分（例如，隔离环304）被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的衬底 侧壁（324）与单晶面。 单侧垂直沟槽晶体管可以形成在平坦侧壁上。 形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。 此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。

公开(公告)号：US6096664A

公开(公告)日：2000-08-01

申请号：US130324

申请日：1998-08-06

申请人： Thomas S. Rupp ,  Stephan Kudelka ,  Jeffrey Gambino ,  Mary Weybright

发明人： Thomas S. Rupp ,  Stephan Kudelka ,  Jeffrey Gambino ,  Mary Weybright

IPC分类号： H01L21/308 ,  H01L21/334 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823462

摘要： A method for forming a pair of MOSFETs in different electrically isolated regions of a silicon substrate. Each one of the MOSFETs has a different gate oxide thickness. A first layer of silicon dioxide is grown to a predetermined thickness over the surface of the silicon substrate. One portion of the silicon dioxide layer is over a first isolated region and another portion of the silicon dioxide layer being over a second isolated region. An inorganic layer is formed over the silicon dioxide layer extending over the isolated regions of the silicon substrate. A first portion of the inorganic layer is over the first isolated regions and a second portion of the inorganic layer is over the second isolated regions. A photoresist layer is formed over the inorganic layer. The photoresist layer is patterned with a window over the first portion of the inorganic layer. The photoresist layer covers the second portion of the inorganic layer. The inorganic layer is patterned into an inorganic mask by bringing a etch into contact with the patterned photoresist layer to selectively remove the first portion of the inorganic layer an thereby expose an underlying portion of the surface of the silicon substrate while leaving the second portion of the inorganic layer. The inorganic mask is used to selectively remove exposed portions of the grown silicon dioxide. The inorganic mask is removed. A second layer of silicon dioxide is grown over the exposed underlying portion of the silicon substrate to a thickness different from the thickness of the first layer of silicon dioxide. The silicon dioxide layers are patterned into gate oxides for each of a corresponding one of the pair of MOSFETs.

摘要翻译： 一种用于在硅衬底的不同电隔离区域中形成一对MOSFET的方法。 每个MOSFET具有不同的栅极氧化物厚度。 在硅衬底的表面上生长第一层二氧化硅至预定厚度。 二氧化硅层的一部分在第一隔离区上方，二氧化硅层的另一部分在第二隔离区之上。 在硅衬底的隔离区域上延伸的二氧化硅层之上形成无机层。 无机层的第一部分在第一隔离区之上，无机层的第二部分在第二隔离区之上。 在无机层上形成光致抗蚀剂层。 在无机层的第一部分上的窗口对光致抗蚀剂层进行图案化。 光致抗蚀剂层覆盖无机层的第二部分。 通过使蚀刻与图案化的光致抗蚀剂层接触来将无机层图案化成无机掩模，以选择性地去除无机层的第一部分，从而暴露硅衬底的表面的下面部分，同时留下第二部分的 无机层。 无机掩模用于选择性地去除生长的二氧化硅的暴露部分。 去除无机掩模。 第二层二氧化硅在硅衬底的暴露下面的部分上生长到与第一层二氧化硅的厚度不同的厚度。 将二氧化硅层图案化成对于一对MOSFET中的每一个的栅极氧化物。

公开(公告)号：US6066527A

公开(公告)日：2000-05-23

申请号：US361055

申请日：1999-07-26

申请人： Stephan Kudelka ,  Alexander Michaelis

发明人： Stephan Kudelka ,  Alexander Michaelis

IPC分类号： H01L21/306 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10861

摘要： In accordance with the present invention, a method for etching back filler material for a buried strap for deep trench capacitors includes the steps of forming a trench in a substrate, filling the trench with a first filler material, recessing the first filler material to a predetermined depth relative to a dielectric collar formed in the trench, forming a divot by etching back the dielectric collar, depositing a liner over the first filler material and portions of the substrate exposed by the formation of the trench, and depositing a second filler material on the liner. A surface of the second filler material is prepared by etching the surface with a wet etchant to provide a hydrogen terminated silicon surface. Wet etching the second filler material is performed to etch back the second filler material selective to the liner and the substrate. The second filler material is etched to form a buried strap.

摘要翻译： 根据本发明，用于深沟槽电容器的掩埋带的填充材料的回填方法包括以下步骤：在衬底中形成沟槽，用第一填充材料填充沟槽，将第一填充材料凹入预定的 相对于形成在沟槽中的介电轴颈的深度，通过蚀刻回介质轴环，在第一填充材料上沉积衬垫和衬底的部分通过形成沟槽而暴露的衬底，并将沉积第二填料 衬垫。 通过用湿蚀刻剂蚀刻该表面以提供氢封端的硅表面来制备第二填料的表面。 执行湿蚀刻第二填充材料以蚀刻对衬垫和衬底有选择性的第二填充材料。 第二填充材料被蚀刻以形成掩埋带。

公开(公告)号：US20070235786A1

公开(公告)日：2007-10-11

申请号：US11399597

申请日：2006-04-07

申请人： Christian Kapteyn ,  Stephan Kudelka

发明人： Christian Kapteyn ,  Stephan Kudelka

IPC分类号： H01L31/119 ,  H01L29/94 ,  H01L29/76 ,  H01L27/108

CPC分类号： H01L29/945 ,  H01L27/10829 ,  H01L27/10861 ,  H01L28/75

摘要： A storage capacitor, particularly for use in a storage cell, exhibits two storage electrodes and a dielectric arranged between the two storage electrodes, an intermediate layer essentially consisting of carbon.

摘要翻译： 特别是用于存储单元的存储电容器具有两个存储电极和布置在两个存储电极之间的电介质，中间层基本上由碳构成。

公开(公告)号：US07273790B2

公开(公告)日：2007-09-25

申请号：US10901406

申请日：2004-07-27

申请人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sänger

发明人： Stephan Kudelka ,  Martin Popp ,  Harald Seidl ,  Annette Sänger

IPC分类号： H01L21/20

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181

摘要： Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

摘要翻译： 在衬底中制造具有绝缘套环的沟槽电容器，其在一侧通过埋入触点电连接，特别地，用于具有衬底中的平面选择晶体管并通过埋入触点连接的半导体存储器单元包括提供 在硬掩模中使用开口的沟槽，在下部和中部沟槽区域中提供电容器电介质，在中央和上部沟槽区域中的套环，以及至少与绝缘套环顶部一样的导电填充物，完全用一个 填充材料，执行STI沟槽制造工艺，去除填充材料并将填充物下沉到轴环顶部以下，在轴环上方的一侧上形成绝缘区域; 露出套环上方不同侧的连接区域，并通过沉积和蚀刻金属填充物来形成掩埋触点。