公开(公告)号：US10445287B2

公开(公告)日：2019-10-15

申请号：US14400557

申请日：2013-09-12

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F15/167 ,  H04L12/773 ,  H04L12/933 ,  G06F15/78 ,  H04L12/937

Abstract: Techniques described herein generally include methods and systems related to circuit switching in a network-on-chip. According to embodiments of the disclosure, a network-on-chip may include routers configured to pre-reserve circuit-switched connections between a source node and a destination node before requested data are available for transmission from the source node to the destination node. Because the circuit-switched connection is already established between the source node and the destination node when the requested data are available for transmission from the source node, the data can be transmitted without the delay or with reduced delay caused by setup overhead of the circuit-switched connection. A connection setup message may be transmitted together with a memory request from the destination node to facilitate pre-reservation of the circuit-switched connection.

公开(公告)号：US10176107B2

公开(公告)日：2019-01-08

申请号：US15300272

申请日：2014-03-29

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0895 ,  G11C11/406 ,  G06F1/32 ,  G06F12/0802

Abstract: Techniques described herein generally include methods and systems related to dynamic cache-sizing used to reduce the energy consumption of a DRAM cache in a chip multiprocessor. Dynamic cache sizing may be performed by adjusting the refresh interval of a DRAM cache or by combining way power-gating of the DRAM cache with adjusting the refresh interval.

公开(公告)号：US09916255B2

公开(公告)日：2018-03-13

申请号：US14567278

申请日：2014-12-11

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897 ,  G06F11/14 ,  G06F12/0804

CPC classification number: G06F12/1009 ,  G06F11/1446 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0897 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/311 ,  G06F2212/502 ,  G06F2212/657

Abstract: Technologies are generally described for methods and systems effective to store data in a memory module. The memory module may include a volatile portion and a non-volatile portion. The methods may comprise receiving, by a processor, a request to store the data. The request may include an indication of a virtual address. The methods may further include determining, by the processor, a persistency of the data based on the virtual address. The methods may further include performing a first operation of identifying a particular portion of the memory module based on the virtual address. The methods may further include generating a command to store the data in the particular portion of the memory module. The methods may further include controlling the operating system to perform a second operation of updating a translation lookaside buffer to indicate the persistency of the data.

公开(公告)号：US09710303B2

公开(公告)日：2017-07-18

申请号：US14009750

申请日：2013-06-06

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC

Inventor： Yan Solihin

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/084 ,  G06F12/0842

CPC classification number: G06F9/4856 ,  G06F12/084 ,  G06F12/0842 ,  Y02D10/13 ,  Y02D10/24 ,  Y02D10/32

Abstract: Technologies are generally described for methods, systems, and processors effective to migrate a thread. The thread may be migrated from the first core to the second core. The first and the second core may be configured in communication with a first cache. The first core may generate a request for a first data block from the first cache. In response to a cache miss in the first cache for the first data block, the first core may generate a request for the first data block from a memory. The first core may coordinate with a second cache to store the first data block in the second cache. The thread may be migrated from the second core to a third core. The second core and third core may be configured in communication with the second cache.

公开(公告)号：US09684603B2

公开(公告)日：2017-06-20

申请号：US14603277

申请日：2015-01-22

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/08 ,  G06F12/0891

CPC classification number: G06F12/0891 ,  G06F12/0837 ,  G06F12/0879 ,  G06F2212/1044 ,  G06F2212/6042 ,  Y02D10/13

Abstract: Techniques are generally described for cache management in a processor with a cache. In response to receiving a bulk memory modification instruction, data blocks of the cache associated with the bulk memory modification instruction may be identified. A cache coherence state of the identified data blocks may also be identified. The updated cache coherence state may be indicative of a zero value of the data blocks and the cache coherence state of the identified data blocks may be updated without modification to a cache data array.

公开(公告)号：US09612961B2

公开(公告)日：2017-04-04

申请号：US14363792

申请日：2013-08-29

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/08 ,  G06F12/0842 ,  G06F1/32 ,  G06F12/0875 ,  G06F12/126 ,  G06F15/173 ,  G06F9/50

CPC classification number: G06F12/0842 ,  G06F1/32 ,  G06F9/5077 ,  G06F12/08 ,  G06F12/0848 ,  G06F12/0875 ,  G06F12/12 ,  G06F12/126 ,  G06F12/128 ,  G06F15/17381 ,  G06F15/781 ,  G06F2212/282 ,  G06F2212/452 ,  G06F2212/6012 ,  G06F2212/69 ,  Y02D10/13 ,  Y02D10/22 ,  Y02D10/36

Abstract: Techniques described herein generally include methods and systems related to cache partitioning in a chip multiprocessor. Cache-partitioning for a single thread or application between multiple data sources improves energy or latency efficiency of a chip multiprocessor by exploiting variations in energy cost and latency cost of the multiple data sources. Partition sizes for each data source may be selected using an optimization algorithm that minimizes or otherwise reduces latencies or energy consumption associated with cache misses.

公开(公告)号：US09552295B2

公开(公告)日：2017-01-24

申请号：US13880194

申请日：2012-09-25

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F12/02

CPC classification number: G06F12/0826 ,  G06F12/023 ,  G06F12/08 ,  G06F12/12 ,  G06F12/121 ,  Y02D10/13

Abstract: Technologies are described herein for improving performance and energy efficiency in a computing system while using a large memory page size. Some example technologies may configure a main memory of the computing system to include a page-to-chunk table and a data area. The page-to-chunk table may include multiple entries such as a first entry. The first entry may correspond to a page that is made up of multiple chunks. The first entry may include pointers to the multiple chunks stored in the data area.

Abstract translation: 这里描述了用于在使用大的存储器页面大小的同时在计算系统中提高性能和能量效率的技术。 一些示例性技术可以将计算系统的主存储器配置为包括页到块表和数据区。 页面到块表可以包括诸如第一条目的多个条目。 第一个条目可以对应于由多个块组成的页面。 第一条目可以包括指向存储在数据区域中的多个块的指针。

公开(公告)号：US09391927B2

公开(公告)日：2016-07-12

申请号：US13995411

申请日：2013-03-20

Applicant: Empire Technology Development LLC

Inventor： Yan Solihin

IPC: H04L12/931 ,  H04L12/933 ,  H04L12/24

CPC classification number: H04L49/40 ,  H04L41/0893 ,  H04L49/109

Abstract: Technologies generally described herein relate to systems and methods effective to control an operating frequency of routers in a multicore processor. Heterogeneous routers in a multicore processor with different maximum operating frequencies may be clustered together to form groups of routers with homogenous assigned operating frequencies. The groups may be used to identify paths to send packets from a first router to a second router along one or more paths.

Abstract translation: 这里通常描述的技术涉及有效地控制多核处理器中的路由器的操作频率的系统和方法。 具有不同最大工作频率的多核处理器中的异构路由器可以集群在一起以形成具有均匀分配的工作频率的路由器组。 这些组可用于识别沿着一个或多个路径从第一路由器向第二路由器发送分组的路径。

公开(公告)号：US09229865B2

公开(公告)日：2016-01-05

申请号：US13982620

申请日：2013-02-21

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

Inventor： Yan Solihin

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1027

Abstract: Technologies are generally described for methods, systems, and devices effective to implement one-cacheable multi-core architectures. In one example, a multi-core processor that includes a first and second tile may be configured to implement a one-cacheable architecture. The second tile may be configured to generate a request for a data block. The first tile may be configured to receive the request for the data block, and determine that the requested data block is part of a group of data blocks identified as one-cacheable. The first tile may further determine that the requested data block is stored in a first cache in the first tile. The first tile may send the data block from the first cache in the first tile to the second tile, and invalidate the data blocks of the group of data blocks in the first cache in the first tile.

Abstract translation: 技术通常被描述为有效实现单缓存多核架构的方法，系统和设备。 在一个示例中，包括第一和第二瓦片的多核处理器可以被配置为实现单缓存架构。 第二瓦片可以被配置为产生对数据块的请求。 第一瓦片可以被配置为接收对数据块的请求，并且确定所请求的数据块是被识别为单缓存的一组数据块的一部分。 第一瓦片还可以确定所请求的数据块被存储在第一瓦片中的第一高速缓存中。 第一瓦片可以将数据块从第一瓦片中的第一高速缓存发送到第二瓦片，并且使第一瓦片中的第一高速缓存中的数据块组的数据块无效。

公开(公告)号：US20140286179A1

公开(公告)日：2014-09-25

申请号：US14005520

申请日：2013-03-20

Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC

Inventor： Yan Solihin

IPC: H04L12/931 ,  H04L12/26

CPC classification number: H04L49/60 ,  H04L45/60 ,  H04L49/101 ,  H04L49/251 ,  H04L49/252

Abstract: Technologies are generally described for methods and systems effective to implement hybrid routers in multicore architectures. A first tile may include a processor core, a cache configured to be in communication with the processor core and a router configured to be in communication with the cache. The router may be effective to move data with a packet switching channel or a circuit switching channel. The first tile may include switching logic configured to be in communication with the cache and the router. The switching logic may be effective to receive a routing objective that may relate to energy or delay costs in routing data through the network. The switching logic may select one of the packet switching channel or the circuit switching channel to move the data through the network based on the routing objective.

Abstract translation: 技术通常被描述为在多核架构中实现混合路由器有效的方法和系统。 第一瓦片可以包括处理器核心，被配置为与处理器核心通信的高速缓存器和配置为与高速缓存通信的路由器。 路由器可能有效地利用分组交换信道或电路交换信道来移动数据。 第一瓦片可以包括被配置为与高速缓存和路由器通信的交换逻辑。 切换逻辑可以有效地接收可能涉及通过网络路由数据的能量或延迟成本的路由目标。 切换逻辑可以选择分组交换信道或电路交换信道中的一个，以基于路由目的通过网络移动数据。