公开(公告)号：US06899857B2

公开(公告)日：2005-05-31

申请号：US10012298

申请日：2001-11-13

申请人： Soo Choi Pheng ,  Lap Chan ,  Wang Cui Yang ,  Siew Yong Kong ,  Alex See

发明人： Soo Choi Pheng ,  Lap Chan ,  Wang Cui Yang ,  Siew Yong Kong ,  Alex See

IPC分类号： C08J9/28 ,  H01L21/316 ,  H01L21/768 ,  C01B33/12 ,  C03C3/00 ,  C04B35/14 ,  C04B38/00

CPC分类号： C08J9/28 ,  C08J2201/0504 ,  C08J2383/00 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/31695 ,  H01L21/7682

摘要： A method for forming a region of low dielectric constant nanoporous material is disclosed. In one embodiment, the present method includes the step of preparing a microemulsion. The method of the present embodiment then recites applying the microemulsion to a surface above which it is desired to form a region of low dielectric constant nanoporous material. Next, the present method recites subjecting the microemulsion, which has been applied to the surface, to a thermal process such that the region of low dielectric constant nanoporous material is formed above the surface.

摘要翻译： 公开了一种形成低介电常数纳米多孔材料区域的方法。 在一个实施方案中，本发明的方法包括制备微乳液的步骤。 本实施例的方法然后将微乳液应用于其上希望形成低介电常数纳米多孔材料区域的表面。 接下来，本方法叙述了将施加到表面的微乳液进行热处理，使得低介电常数纳米多孔材料的区域形成在表面上方。

公开(公告)号：US06890854B2

公开(公告)日：2005-05-10

申请号：US09726903

申请日：2000-11-29

申请人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

发明人： Pooi See Lee ,  Kin Leong Pey ,  Alex See ,  Lap Chan

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L29/49 ,  H01L21/26

CPC分类号： H01L29/665 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/4933

摘要： A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into the processed substrate; depositing nickel onto the processed substrate; annealing the processed substrate so as to form nickel mono-silicide; removing the unreacted nickel; and performing a series procedures to complete integrated circuit fabrication. This nickel salicide process increases the annealing temperature range for which a continuous, thin nickel mono-silicide layer can be formed on silicon by salicidation. It also delays the onset of agglomeration of nickel mono-silicide thin-films to a higher annealing temperature. Moreover, this nickel salicide process delays the transformation from nickel mono-silicide to higher resistivity nickel di-silicide, to higher annealing temperature. It also reduces nickel enhanced poly-silicon grain growth to prevent layer inversion. Some embodiments of this nickel salicide process may be used in an otherwise standard salicide process, to form integrated circuit devices with low resistivity transistor gate electrodes and source/drain contacts.

摘要翻译： 公开了一种用于进行镍盐化的方法和装置。 镍硅化物工艺通常包括：形成包括部分制造的集成电路部件和硅衬底的处理衬底; 将氮气掺入经处理的基底中; 将镍沉积在经处理的基底上; 对经处理的基板退火以形成单一硅化镍; 去除未反应的镍; 并执行串联程序来完成集成电路制造。 该镍硅化物工艺增加了退火温度范围，通过盐化可在硅上形成连续的薄镍单硅化物层。 它还延迟了单一硅化镍薄膜的聚集开始到更高的退火温度。 此外，该镍硅化物工艺延迟了从单一硅化镍到更高电阻率的二硅化镍的转变到更高的退火温度。 它还减少了镍增强的多晶硅晶粒生长，以防止层反转。 这种镍硅化物工艺的一些实施例可以用于另外标准的自对准硅化物工艺中，以形成具有低电阻率晶体管栅电极和源极/漏极接触的集成电路器件。

公开(公告)号：US06878623B2

公开(公告)日：2005-04-12

申请号：US10457885

申请日：2003-06-09

申请人： Cheng Cheh Tan ,  Randall Cher Liang Cha ,  Alex See ,  Lap Chan

发明人： Cheng Cheh Tan ,  Randall Cher Liang Cha ,  Alex See ,  Lap Chan

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L29/66507 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656

摘要： A gate structure having associated (LDD) regions and source and drain is formed as is conventional. A first oxide spacer, for example, is formed along the sidewalls of the gate structure. A layer of metal such as titanium is then deposited over the surface of the gate structure. Second sidewall spacers are formed covering the metal over the first sidewall spacer and covering the metal over isolation regions. A layer of polysilicon is deposited over the surface of the gate structure. A rapid thermal annealing (RTA) is performed causing the metal to react with both the silicon in the junction below the metal and the polysilicon above the metal forming a metal silicide. Metal along the sidewalls between the first and second sidewall spacers and over the isolation regions does not react and is etched away. By providing an additional source of silicon in the polysilicon layer above the metal, a thicker silicide is achieved.

摘要翻译： 具有相关联（LDD）区域和源极和漏极的栅极结构如常规形成。 例如，沿着栅极结构的侧壁形成第一氧化物间隔物。 然后在栅极结构的表面上沉积诸如钛的金属层。 形成第二侧壁间隔物，覆盖第一侧壁间隔物上的金属，并将金属覆盖在隔离区上。 在栅极结构的表面上沉积多晶硅层。 进行快速热退火（RTA），使得金属与金属之下的结中的硅和形成金属硅化物的金属上方的多晶硅反应。 沿着第一和第二侧壁间隔物之间​​的侧壁以及隔离区域上的金属不会反应并被蚀刻掉。 通过在金属上方的多晶硅层中提供附加的硅源，可获得更厚的硅化物。

公开(公告)号：US06613652B2

公开(公告)日：2003-09-02

申请号：US09805707

申请日：2001-03-14

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

IPC分类号： H01L2130

CPC分类号： H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L27/12

摘要： A method to form SOI devices using wafer bonding. A first substrate is provided having trenches in a first side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to form isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.

公开(公告)号：US06492242B1

公开(公告)日：2002-12-10

申请号：US09609447

申请日：2000-07-03

申请人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

发明人： Alex See ,  Cher Liang Randall Cha ,  Shyuz Fong Quek ,  Ting Cheong Ang ,  Wye Boon Loh ,  Sang Yee Loong ,  Jun Song ,  Chua Chee Tee

IPC分类号： H01L2120

CPC分类号： H01L28/40 ,  H01L21/31683

摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.

摘要翻译： 在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化， 已经开发 该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。 激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度 。 第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域， 通过覆盖光刻板中的透明区域。 该过程还导致在下面的金属层的顶部上形成高K层。

公开(公告)号：US06475875B1

公开(公告)日：2002-11-05

申请号：US09900410

申请日：2001-07-09

申请人： Pang Chong Hau ,  Chen Feng ,  Alex See ,  Peter Hing

发明人： Pang Chong Hau ,  Chen Feng ,  Alex See ,  Peter Hing

IPC分类号： H01L2176

CPC分类号： H01L21/76227 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/76224

摘要： A process for forming insulator filled, shallow trench isolation (STI), regions in a semiconductor substrate, featuring a disposable polysilicon stop layer used to allow uniform insulator fill to be obtained, independent of shallow trench width, has been developed. The process features filling shallow trench shapes with a first high density plasma (HDP), deposited silicon oxide layer, followed by the deposition of the thin polysilicon stop layer, and a second HDP silicon oxide layer. After a planarizing chemical mechanical polishing procedure residual regions of the second HDP silicon oxide, still remaining in regions overlying the insulator filled shallow trench shapes, are selectively removed using the thin polysilicon layer as a stop layer. The polysilicon layer is then thermally oxidized. The thickness of the polysilicon layer can be varied such that the resultant polysilicon oxide layer serves to alleviate the possible oxide loss in the STI regions during subsequent clean processes.

摘要翻译： 已经开发了用于形成绝缘体填充的浅沟槽隔离（STI）的方法，半导体衬底中的区域，其特征在于用于允许获得均匀的绝缘体填充的一次性多晶硅停止层，而与浅沟槽宽度无关。 该工艺特征是用第一高密度等离子体（HDP），沉积的氧化硅层填充浅沟槽形状，随后沉积薄多晶硅停止层和第二HDP氧化硅层。 在平坦化化学机械抛光程序之后，仍然保留在覆盖绝缘体填充的浅沟槽形状的区域中的第二HDP氧化硅的残余区域使用薄多晶硅层作为停止层选择性地去除。 然后将多晶硅层热氧化。 可以改变多晶硅层的厚度，使得所得到的多晶硅氧化物层用于在随后的清洁工艺期间减轻STI区域中可能的氧化物损失。

公开(公告)号：US06472697B2

公开(公告)日：2002-10-29

申请号：US10140574

申请日：2002-05-08

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

IPC分类号： H01L2710

CPC分类号： H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

公开(公告)号：US06468880B1

公开(公告)日：2002-10-22

申请号：US09805954

申请日：2001-03-15

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Tae Jong Lee ,  Wang Ling Goh

IPC分类号： H01L2130

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  Y10S438/977

摘要： A method to form a silicon on insulator (SOI) device using wafer bonding. A first substrate is provided having an insulating layer over a first side. A second substrate is provided having first isolation regions (e.g., STI) that fill first trenches in the second substrate. Next, we bond the first and second substrate together by bonding the insulating layer to the first isolation regions and the second substrate. Then, a stop layer is formed over the second side of the second substrate. The stop layer and the second side of the second substrate are patterned to form second trenches in the second substrate. The second trenches have sidewalls at least partially defined by the isolation regions and the second trenches expose the second insulating layer. The second trenches define first active regions over the first isolation regions (STI) and define second active regions over the insulating layer. Next, the second trenches are filled with an insulator material to from second isolation regions. Next, the stop layer is removed. Lastly, devices are formed in and on the active regions.

摘要翻译： 一种使用晶片接合形成绝缘体上硅（SOI）器件的方法。 提供第一基板，其在第一侧上具有绝缘层。 提供了第二衬底，其具有填充第二衬底中的第一沟槽的第一隔离区域（例如STI）。 接下来，通过将绝缘层粘合到第一隔离区域和第二基板上，将第一和第二基板结合在一起。 然后，在第二基板的第二侧上形成止挡层。 图案化第二基板的阻挡层和第二侧，以在第二基板中形成第二沟槽。 第二沟槽具有由隔离区域至少部分地限定的侧壁，并且第二沟槽露出第二绝缘层。 第二沟槽限定第一隔离区域（STI）上的第一有源区，并在绝缘层上限定第二有源区。 接下来，第二沟槽用绝缘体材料填充到第二隔离区域。 接下来，停止层被去除。 最后，在活动区域​​中形成器件。

公开(公告)号：US06432797B1

公开(公告)日：2002-08-13

申请号：US09768487

申请日：2001-01-25

申请人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Yeow Kheng Lim

发明人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Yeow Kheng Lim

IPC分类号： H01L2176

CPC分类号： H01L21/76237 ,  H01L21/31053 ,  H01L21/31055

摘要： A method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is described. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying the semiconductor substrate has been removed wherein the portion of the oxide layer remaining provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication of an integrated circuit device.

摘要翻译： 描述了形成浅沟槽隔离的方法，其中在隔离和有源区的边缘处的氧化物凹陷被减少或消除。 将沟槽蚀刻到半导体衬底中。 沉积在半导体衬底上并填充沟槽的氧化物层。 将氮原子注入到覆盖沟槽的氧化物层中。 将衬底退火，由此在覆盖沟槽的氧化物层的表面上形成一层富氮氧化物。 氧化物层平坦化到半导体衬底，其中富氧氧化物层平坦化比氧化物层缓慢，导致一部分氧化物层保留在沟槽上方，在氧化物层覆盖半导体衬底之后，其中部分 剩余的氧化物层在浅沟槽隔离和有源区域之间提供平滑的过渡，从而在集成电路器件的制造中完成浅沟槽隔离的形成。

公开(公告)号：US06399471B1

公开(公告)日：2002-06-04

申请号：US09783379

申请日：2001-02-15

申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

IPC分类号： H01L2144

CPC分类号： H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.