公开(公告)号：US06577009B1

公开(公告)日：2003-06-10

申请号：US09776718

申请日：2001-02-06

申请人： Lu You ,  Fei Wang ,  Minh Van Ngo

发明人： Lu You ,  Fei Wang ,  Minh Van Ngo

IPC分类号： H01L2352

CPC分类号： H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material.as the first diffusion barrier layer. The first diffusion barrier layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。 通孔也可以有圆角。 侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由第一扩散阻挡层中的相同材料形成。 第一扩散阻挡层可以由碳化硅形成。 还公开了制造半导体器件的方法。

公开(公告)号：US06475847B1

公开(公告)日：2002-11-05

申请号：US10109526

申请日：2002-03-27

申请人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

发明人： Minh Van Ngo ,  Yu Sun ,  Fei Wang ,  Mark T. Ramsbey ,  Chi Chang ,  Angela T. Hui ,  Mark S. Chang

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/115 ,  H01L2924/3011

摘要： A method for shrinking a semiconductor device and minimizing auto-doping problem is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

摘要翻译： 公开了一种缩小半导体器件并最小化自动掺杂问题的方法。 蚀刻停止层被消除并且被可消耗的衬垫氧化物层代替，使得该器件的层叠栅极结构可以被更靠近地放置在一起，从而允许器件收缩。 衬垫氧化物层直接形成在衬底上并与堆叠的栅极结构，侧壁间隔物以及形成在衬底上的源极和漏极接触，并且用作电介质层的自动掺杂势垒，以防止形成在衬底中的硼和磷 电介质层自动掺入源和漏极。

公开(公告)号：US08202810B2

公开(公告)日：2012-06-19

申请号：US11971331

申请日：2008-01-09

申请人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

发明人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

IPC分类号： H01L21/31

CPC分类号： H01L21/76877 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76883 ,  Y10S438/902

摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

摘要翻译： 一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化 ，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

公开(公告)号：US20120038051A1

公开(公告)日：2012-02-16

申请号：US13281491

申请日：2011-10-26

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US07786003B1

公开(公告)日：2010-08-31

申请号：US11136569

申请日：2005-05-25

申请人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

发明人： Arvind Halliyal ,  Zoran Krivokapic ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Minh Van Ngo ,  Mark T. Ramsbey ,  Jeffery A. Shields ,  Jusuke Ogura

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/743 ,  H01L21/76895

摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.

摘要翻译： 掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。 硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。 在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。 然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。 凹槽里填充有抛光的填充材料。 然后去除硬掩模以形成硅化物掩埋的局部互连。

公开(公告)号：US07632706B2

公开(公告)日：2009-12-15

申请号：US11256558

申请日：2005-10-21

申请人： Nicolay F. Yudanov ,  Igor Sokolik ,  Richard P. Kingsborough ,  William G. Leonard ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Minh Van Ngo

发明人： Nicolay F. Yudanov ,  Igor Sokolik ,  Richard P. Kingsborough ,  William G. Leonard ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Minh Van Ngo

IPC分类号： H01L51/40

CPC分类号： H01L51/001 ,  C23C16/54 ,  H01J2237/3321 ,  H01L27/285

摘要： A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system can further employ a second electrode formation component operative to form a second electrode on the organic semiconductor layer.

摘要翻译： 公开了一种用于处理有机存储单元的系统和方法。 示例性系统可以采用封闭的处理室，可操作以在第一电极上形成钝化层的无源层形成部件和可操作地在被动层上形成有机半导体层的有机半导体层形成部件。 晶片衬底不需要从钝化层形成系统转移到有机半导体层形成系统。 钝化层在形成无源层之后并且在形成有机半导体层之前不暴露于空气。 结果，在薄膜层中不会发生由暴露于空气引起的导电杂质，从而提高了有机存储器件的生产率，质量和可靠性。 该系统可以进一步采用可在有机半导体层上形成第二电极的第二电极形成部件。

公开(公告)号：US07312125B1

公开(公告)日：2007-12-25

申请号：US10773026

申请日：2004-02-05

申请人： Qi Xiang ,  Paul R. Besser ,  Minh Van Ngo ,  Eric N. Paton ,  Haihong Wang

发明人： Qi Xiang ,  Paul R. Besser ,  Minh Van Ngo ,  Eric N. Paton ,  Haihong Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L27/1203 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684 ,  Y10S438/938

摘要： An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and a buried oxide layer. A hydrogen implant can provide a breaking interface to remove a silicon substrate from the silicon germanium layer.

摘要翻译： 集成电路包括多层。 可以使用绝缘体上半导体（SOI）晶片来容纳晶体管。 可以结合两个基板或晶片以形成多个层。 应变半导体层可以在硅锗层和掩埋氧化物层之间。 氢注入可以提供断开界面以从硅锗层去除硅衬底。

公开(公告)号：US07074677B1

公开(公告)日：2006-07-11

申请号：US10307189

申请日：2002-11-29

申请人： Arvind Halliyal ,  Minh Van Ngo ,  Hidehiko Shiraiwa ,  Rinji Sugino

发明人： Arvind Halliyal ,  Minh Van Ngo ,  Hidehiko Shiraiwa ,  Rinji Sugino

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  Y10S438/954

摘要： A manufacturing method for a Flash memory includes depositing a first dielectric layer on a semiconductor substrate. A low hydrogen charge-trapping dielectric layer is deposited followed by a second dielectric layer. First and second bitlines are implanted and a wordline layer is deposited.

摘要翻译： 一种闪速存储器的制造方法，包括在半导体衬底上沉积第一介电层。 沉积低氢电荷捕获电介质层，然后沉积第二介电层。 植入第一和第二位线，并存放字线层。

公开(公告)号：US07023046B2

公开(公告)日：2006-04-04

申请号：US10617450

申请日：2003-07-11

申请人： Minh Van Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yee-Mei Yang ,  Robert A. Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

发明人： Minh Van Ngo ,  Angela Hui ,  Ning Cheng ,  Jeyong Park ,  Jean Yee-Mei Yang ,  Robert A. Huertas ,  Tazrien Kamal ,  Pei-Yuan Gao ,  Tyagamohan Gottipati

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625 ,  H01L27/115 ,  H01L29/511

摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

摘要翻译： 具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。 实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在 相同的沉积室。

公开(公告)号：US07005357B2

公开(公告)日：2006-02-28

申请号：US10756023

申请日：2004-01-12

申请人： Minh Van Ngo ,  Simon Siu-Sing Chan ,  Paul R. Besser ,  Paul L. King ,  Errol Todd Ryan ,  Robert J. Chiu

发明人： Minh Van Ngo ,  Simon Siu-Sing Chan ,  Paul R. Besser ,  Paul L. King ,  Errol Todd Ryan ,  Robert J. Chiu

IPC分类号： H01L21/336 ,  H01L21/441

CPC分类号： H01L29/6659 ,  H01L29/665

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。