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41 条记录 (耗时 0.05 秒)

    Method using monolayer etch masks in combination with printed masks
    34.
    发明授权
    Method using monolayer etch masks in combination with printed masks 失效
    使用单层蚀刻掩模与印刷掩模组合的方法

    公开(公告)号：US07524768B2

    公开(公告)日：2009-04-28

    申请号：US11388718

    申请日：2006-03-24

    申请人： Eugene M. Chow ,  William S. Wong ,  Michael Chabinyc ,  Jeng Ping Lu ,  Ana Claudia Arias

    发明人： Eugene M. Chow ,  William S. Wong ,  Michael Chabinyc ,  Jeng Ping Lu ,  Ana Claudia Arias

    IPC分类号： H01L21/302

    CPC分类号： H01L21/302 ,  H01L21/0271 ,  H01L21/0273 ,  H01L27/124 ,  H01L27/1288 ,  H01L27/1292 ,  H01L29/66765

    摘要： A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.

    摘要翻译： 将薄膜图案尺寸小于印刷像素掩模尺寸的方法。 印刷的掩模沉积在基底上的薄膜上。 第二掩模层选择性地沉积在膜上，而不是印刷在掩模上。 然后将第三掩模印刷到基底上以对第二掩模的一部分进行图案化。 然后使用某些溶剂去除印刷的掩模，而不是薄膜上的掩模层。 然后将掩模层与蚀刻结合在薄膜上形成图案。 形成在薄膜中的特征小于印刷掩模的最小尺寸。 涂覆的掩模层可以是选择性地结合薄膜的自组装单层或其它材料。

    Additive Printed Mask Process And Structures Produced Thereby
    35.
    发明申请
    Additive Printed Mask Process And Structures Produced Thereby 有权
    添加剂印花面膜工艺和结构

    公开(公告)号：US20080153014A1

    公开(公告)日：2008-06-26

    申请号：US12046242

    申请日：2008-03-11

    申请人： William Wong ,  Scott Limb ,  Michael Chabinyc ,  Beverly Russo ,  Rene A. Lujan

    发明人： William Wong ,  Scott Limb ,  Michael Chabinyc ,  Beverly Russo ,  Rene A. Lujan

    IPC分类号： G03F1/06

    CPC分类号： G02F1/133512 ,  B41M3/003 ,  B41M3/006 ,  G02F1/133516 ,  G03F7/2018 ,  Y10S438/942

    摘要： A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.

    摘要翻译： 数字光刻工艺首先沉积由印刷图案掩模特征组成的掩模层。 印刷图案掩模特征限定了可以沉积目标材料的间隙，优选通过数字光刻工艺。 如果需要，目标材料被固化或硬化成目标特征。 然后选择性地去除掩模层。 剩余的目标特征然后可以用作曝光或蚀刻掩模，诸如流体容纳元件的物理结构等。可以在实现数字光刻的优点的同时获得精细特征宽度，更小的打印图案化掩模特征的最小宽度 制造过程。

    Additive printed mask process and structures produced thereby
    36.
    发明授权
    Additive printed mask process and structures produced thereby 有权
    添加印刷掩模工艺和由此生产的结构

    公开(公告)号：US07365022B2

    公开(公告)日：2008-04-29

    申请号：US10536102

    申请日：2006-01-20

    申请人： William Wong ,  Scott Limb ,  Michael Chabinyc ,  Beverly Russo ,  Rene A. Lujan

    发明人： William Wong ,  Scott Limb ,  Michael Chabinyc ,  Beverly Russo ,  Rene A. Lujan

    IPC分类号： H01L21/31

    CPC分类号： G02F1/133512 ,  B41M3/003 ,  B41M3/006 ,  G02F1/133516 ,  G03F7/2018 ,  Y10S438/942

    摘要： A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.

    摘要翻译： 数字光刻工艺首先沉积由印刷图案掩模特征组成的掩模层。 印刷图案掩模特征限定了可以沉积目标材料的间隙，优选通过数字光刻工艺。 如果需要，目标材料被固化或硬化成目标特征。 然后选择性地去除掩模层。 剩余的目标特征然后可以用作曝光或蚀刻掩模，诸如流体容纳元件的物理结构等。可以在实现数字光刻的优点的同时获得精细特征宽度，更小的打印图案化掩模特征的最小宽度 制造过程。

    Self-Forming Microlenses For VCSEL Arrays
    37.
    发明申请
    Self-Forming Microlenses For VCSEL Arrays 失效
    VCSEL阵列的自形成微透镜

    公开(公告)号：US20080096298A1

    公开(公告)日：2008-04-24

    申请号：US11954181

    申请日：2007-12-11

    申请人： Michael Chabinyc ,  Patrick Maeda ,  Christopher Chua

    发明人： Michael Chabinyc ,  Patrick Maeda ,  Christopher Chua

    IPC分类号： H01L33/00

    CPC分类号： B82Y30/00 ,  H01S5/0425 ,  H01S5/18388 ,  H01S5/423

    摘要： A Vertical Cavity Surface Emitting Laser (VCSEL) assembly including a VCSEL structure having a light-emitting region located on its surface, a relatively wettable region of a surface modifier coating formed over the light emitting region, and a microlens formed on the relatively wettable region. A relatively non-wettable region of the surface modifier coating is formed around the light-emitting region (e.g., on the electrode surrounding the light-emitting region). The surface modifier coating is formed, for example, from one or more organothiols that change the surface energies of the light-emitting region and/or the electrode to facilitate self-assembly and self-registration of the microlens material. The microlens material is printed, microjetted, or dip coated onto the VCSEL structure such that the microlens material wets to the relatively wettable region, thereby forming a liquid bead that is reliably positioned over the light-emitting region. The liquid bead is then cured to form the microlens.

    摘要翻译： 包括具有位于其表面上的发光区域的VCSEL结构的垂直腔表面发射激光器（VCSEL）组件，形成在发光区域上的表面改性剂涂层的相对可润湿的区域，以及形成在相对可润湿区域上的微透镜 。 在发光区域（例如，围绕发光区域的电极）周围形成表面改性剂涂层的相对不可润湿的区域。 表面改性剂涂层例如由一种或多种改变发光区域和/或电极的表面能的有机硫醇形成，以促进微透镜材料的自组装和自配准。 将微透镜材料印刷，微喷射或浸涂在VCSEL结构上，使得微透镜材料润湿到相对可润湿的区域，从而形成可靠地定位在发光区域上方的液体珠粒。 然后将液体珠固化以形成微透镜。

    Transistor Production Using Semiconductor Printing Fluid
    38.
    发明申请
    Transistor Production Using Semiconductor Printing Fluid 有权
    使用半导体印刷液的晶体管生产

    公开(公告)号：US20080092807A1

    公开(公告)日：2008-04-24

    申请号：US11957384

    申请日：2007-12-14

    申请人： Michael Chabinyc ,  Ana Arias

    发明人： Michael Chabinyc ,  Ana Arias

    IPC分类号： B05C11/02

    CPC分类号： H01L51/0004 ,  B82Y10/00 ,  B82Y30/00 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/283 ,  H01L29/66742 ,  H01L51/0012 ,  H01L51/0541 ,  H01L51/0545

    摘要： A transistor is formed by applying modifier coatings to source and drain contacts and/or to the channel region between those contacts. The modifier coatings are selected to adjust the surface energy pattern in the source/drain/channel region such that semiconductor printing fluid is not drawn away from the channel region. For example, the modifier coatings for the contacts can be selected to have substantially the same surface energy as the modifier coating for the channel region. Semiconductor printing fluid deposited on the channel region therefore settles in place (due to the lack of a surface energy differential) and forms a relatively thick active semiconductor region between the contacts. Alternatively, the modifier coatings can be selected to have lower surface energies than the modifier coating in the channel region, which actually causes semiconductor printing fluid to be drawn towards the channel region.

    摘要翻译： 通过将改性剂涂层施加到源极和漏极触点和/或向这些触点之间的沟道区域施加晶体管。 选择改性剂涂层以调节源极/漏极/沟道区域中的表面能量图案，使得半导体印刷液体不被从通道区域拉出。 例如，可以选择用于触点的改性剂涂层以具有与用于沟道区的改性涂层基本上相同的表面能。 沉积在通道区域上的半导体印刷液体因此沉降就位（由于缺少表面能量差）并且在触点之间形成相对厚的有源半导体区域。 或者，可以选择改性剂涂层以具有比通道区域中的改性剂涂层更低的表面能，其实际上导致半导体印刷液体被拉向通道区域。

    Method of forming a darkfield etch mask
    39.
    发明申请
    Method of forming a darkfield etch mask 失效
    形成暗场蚀刻掩模的方法

    公开(公告)号：US20070235410A1

    公开(公告)日：2007-10-11

    申请号：US11394438

    申请日：2006-03-31

    申请人： William Wong ,  Scott Limb ,  Beverly Russo ,  Michael Chabinyc ,  Rene Lujan

    发明人： William Wong ,  Scott Limb ,  Beverly Russo ,  Michael Chabinyc ,  Rene Lujan

    IPC分类号： C23F1/00

    CPC分类号： B44C1/22 ,  H01L27/1292 ,  H01L29/4908

    摘要： Susceptibility of darkfield etch masks (majority of the mask area is opaque) to pinhole defects, transferred pattern, non-uniformity, etc. due to ejector dropout or drop misdirection, and long duty cycles due to large-area coverage, when using digital lithography (or print patterning) is addressed by using a clear-field print pattern that is then coated with etch resist material. The printed clear field pattern is selectively removed to form an inverse pattern (darkfield) within the coated resist layer. Etching then removes selected portions of an underlying (e.g., encapsulation, conductive, etc.) layer. Removal of the mask produces a layer with large-area features with substantially reduced defects.

    摘要翻译： 当使用数字光刻技术时，由于喷射器脱落或滴落错误导向，暗区蚀刻掩模（大部分掩模区域不透明）对针孔缺陷，转印图案，不均匀性等的敏感性以及由于大面积覆盖而造成的长占空比 （或印刷图案化）通过使用随后涂覆有抗蚀剂材料的透明场印刷图案来解决。 选择性地去除打印的清晰场图案以在涂覆的抗蚀剂层内形成反向图案（暗场）。 然后蚀刻去除底层（例如，封装，导电等）层的选定部分。 去除掩模产生具有大面积特征并具有显着减少的缺陷的层。

    Organic thin-film transistor backplane with multi-layer contact structures and data lines
    40.
    发明申请
    Organic thin-film transistor backplane with multi-layer contact structures and data lines 有权
    具有多层接触结构和数据线的有机薄膜晶体管背板

    公开(公告)号：US20070158644A1

    公开(公告)日：2007-07-12

    申请号：US11316551

    申请日：2005-12-21

    申请人： Michael Chabinyc ,  Rene Lujan ,  Ana Arias ,  Jackson Ho

    发明人： Michael Chabinyc ,  Rene Lujan ,  Ana Arias ,  Jackson Ho

    IPC分类号： H01L29/08

    CPC分类号： H01L27/283 ,  H01L51/0037 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/105

    摘要： A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.

    摘要翻译： 背板电路包括有机薄膜晶体管（OTFT）的阵列，每个OTFT包括源极接触，漏极接触以及在源极和漏极接触之间延伸的有机半导体区域。 每行的漏极触点连接到地址线。 源极和漏极触点和地址线使用包括由相对便宜的金属（例如，铝或铜）形成的相对厚的基部的多层结构以及由高功函数形成的相对较薄的接触层制造， 与有机半导体呈现良好的电接触的低氧化金属（例如，金）形成在与基底的至少一个外表面相对的位置，并且至少部分地位于有机半导体与下面的介电层接触的界面区域中。