公开(公告)号：US07205604B2

公开(公告)日：2007-04-17

申请号：US10463038

申请日：2003-06-17

申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

IPC分类号： H01L29/94

CPC分类号： H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/778 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7789 ,  H01L29/7828

摘要： A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a heterojunction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the heterojunction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

摘要翻译： 描述了形成场效应晶体管，场效应晶体管和CMOS电路的应变垂直沟道的方法，其中在垂直单晶半导体结构的侧壁上结合有漏极，主体和源极区域，其中形成异质结 在晶体管的源极和主体之间，其中源极区域和沟道相对于体区域独立地晶格应变，并且其中漏极区域包含碳掺杂区域以防止掺杂剂（硼）扩散到体内。 本发明通过异质结和晶格应变来减少来自源区的漏电流的问题，同时通过选择半导体材料独立地允许沟道区中的晶格应变以增加迁移率。

公开(公告)号：US07038277B2

公开(公告)日：2006-05-02

申请号：US10826712

申请日：2004-04-16

申请人： Jack Oon Chu ,  Alfred Grill ,  Dean A. Herman, Jr. ,  Katherine L. Saenger

发明人： Jack Oon Chu ,  Alfred Grill ,  Dean A. Herman, Jr. ,  Katherine L. Saenger

IPC分类号： H01L27/01

CPC分类号： H01L27/1203 ,  H01L21/76259

摘要： A method for forming an integrated circuit on an insulating substrate is described comprising the steps of forming a semiconductor layer on a seed wafer substrate containing an at least partially crystalline porous release layer, processing the semiconductor layer to form a “transferable” device layer containing at least one semiconductor device, and bonding said transferable device layer to a final, insulating substrate before or after separating said device layer from the seed wafer substrate. A second method, for separating a semiconductor layer from a seed wafer substrate, is described wherein an at least partially crystalline porous layer initially connecting the semiconductor layer and seed wafer substrate is split or broken apart by the steps of (i) introducing a fluid including water into the pores of said porous layer, and (ii) expanding said fluid by solidifying or freezing to break apart the porous layer. The at least partially crystalline porous layer may incorporate at least one porous silicon germanium alloy layer alone or in combination with at least one porous Si layer. Also described is an integrated circuit comprising the transfered device layer described above.

公开(公告)号：US06909186B2

公开(公告)日：2005-06-21

申请号：US10427233

申请日：2003-05-01

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L21/336 ,  H01L27/12 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7842 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696

摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

摘要翻译： 公开了用于增强的FET器件的制造结构和方法，其中防止掺杂剂杂质通过栅极绝缘体扩散。 该结构包括夹在栅极绝缘体和掺杂有杂质的层之间的Si：C或SiGe：C层，以提供预选的功函数。 还进一步公开了如何以及对FET器件的进一步改进，诸如凸起源极/漏极和绝缘体上的多面绝缘体，绝缘体上的MODFET与应变的基于Si的绝缘体上的技术集成。

公开(公告)号：US06881259B1

公开(公告)日：2005-04-19

申请号：US09633857

申请日：2000-08-07

申请人： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

发明人： David C. Ahlgren ,  Jack Oon Chu ,  Basanth Jagannathan ,  Ryan W. Wuthrich

IPC分类号： C30B25/16 ,  C30B29/52

CPC分类号： C30B29/52 ,  C30B25/165

摘要： Analysis of residual gases from a process for depositing a film containing silicon on a crystalline silicon surface to determine partial pressure of hydrogen evolved during deposition develops a signature which indicates temperature and/or concentration of germanium at the deposition surface. Calibration and collection of hydrogen partial pressure data at a rate which is high relative to film deposition rate allows real-time, in-situ, non-destructive determination of material concentration profile over the thickness of the film and/or monitoring the temperature of a silicon film deposition process with increased accuracy and resolution to provide films of a desired thickness with high accuracy.

摘要翻译： 分析来自用于在晶体硅表面上沉积含硅的膜的工艺的残余气体，以确定在沉积期间释放出来的氢的分压，形成指示沉积表面的锗的温度和/或浓度的标记。 以相对于膜沉积速率高的速率校准和收集氢分压数据允许在膜的厚度上的材料浓度分布的实时，原位，非破坏性测定和/或监测膜的温度 硅膜沉积工艺具有更高的精度和分辨率，以高精度提供所需厚度的膜。

公开(公告)号：US06426265B1

公开(公告)日：2002-07-30

申请号：US09774126

申请日：2001-01-30

申请人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

发明人： Jack Oon Chu ,  Douglas Duane Coolbaugh ,  James Stuart Dunn ,  David R. Greenberg ,  David L. Harame ,  Basanth Jagannathan ,  Robb Allen Johnson ,  Louis D. Lanzerotti ,  Kathryn Turner Schonenberg ,  Ryan Wayne Wuthrich

IPC分类号： H01L21331

CPC分类号： H01L29/66242 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/7378

摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

公开(公告)号：US07790538B2

公开(公告)日：2010-09-07

申请号：US12118689

申请日：2008-05-10

申请人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

发明人： Huiling Shang ,  Meikei Ieong ,  Jack Oon Chu ,  Kathryn W. Guarini

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/7841

摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

摘要翻译： 公开了一种用于压缩应变Ge层中的PFET器件的结构和方法。 这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。 该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。 承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。

公开(公告)号：US20090239097A1

公开(公告)日：2009-09-24

申请号：US12051366

申请日：2008-03-19

申请人： Jack Oon Chu ,  Deborah Ann Neumayer

发明人： Jack Oon Chu ,  Deborah Ann Neumayer

IPC分类号： C30B25/18 ,  B32B9/00

CPC分类号： C30B25/18 ,  C30B29/08 ,  Y10S438/933

摘要： A method is disclosed for preparing a surface of a Group III-Group V compound semiconductor for epitaxial deposition. The III-V semiconductor surface is treated with boron (B) at a temperature of between about 250° C. and about 350° C. A suitable form for supplying B for the surface treatment is diborane. The B treatment can be followed by epitaxial growth, for instance by a Group IV semiconductor, at temperatures similar to those of the B treatment. The method yields high quality heterojunction, suitable for fabricating a large variety of device structures.

摘要翻译： 公开了制备用于外延沉积的III-V族化合物半导体的表面的方法。 III-V族半导体表面在约250℃至约350℃的温度下用硼（B）处理。用于供应B用于表面处理的合适形式是乙硼烷。 B处理可以在与B处理类似的温度下进行外延生长，例如通过IV族半导体。 该方法产生高质量异质结，适用于制造各种器件结构。

公开(公告)号：US07569442B2

公开(公告)日：2009-08-04

申请号：US11158726

申请日：2005-06-22

申请人： Qiqing Christine Ouyang ,  Jack Oon Chu

发明人： Qiqing Christine Ouyang ,  Jack Oon Chu

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/802 ,  Y10S438/933

摘要： A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

摘要翻译： 描述了一种用于形成场效应晶体管，场效应晶体管和CMOS电路的应变横向沟道结构的方法，其在单晶半导体衬底上结合了漏极，主体和源极区域，其中在 晶体管的源极和主体，其中源极区域和沟道独立地相对于身体区域进行晶格应变。 本发明通过异质结和晶格应变来减少来自源极区的漏电流的问题，同时通过选择半导体材料和合金组成独立地允许沟道区域中的晶格应变增加迁移率。

公开(公告)号：US07411214B2

公开(公告)日：2008-08-12

申请号：US11067186

申请日：2005-02-26

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L21/00

CPC分类号： H01L29/785 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7842 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696

摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.

公开(公告)号：US20080132021A1

公开(公告)日：2008-06-05

申请号：US11971392

申请日：2008-01-09

申请人： Jack Oon Chu

发明人： Jack Oon Chu

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/2807 ,  H01L21/28255 ,  H01L29/1029 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7787 ,  H01L29/7842 ,  H01L29/78642 ,  H01L29/78648 ,  H01L29/78684 ,  H01L29/78696

摘要： Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a layer which is doped with impurities in order to provide a preselected workfunction. It is further disclosed how this, and further improvements for FET devices, such as raised source/drain and multifaceted gate on insulator, MODFET on insulator are integrated with strained Si based layer on insulator technology.