公开(公告)号：US09620589B2

公开(公告)日：2017-04-11

申请号：US14246983

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicolas Sassiat ,  Ran Yan ,  Kun-Hsien Lin ,  Jan Hoentschel

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L29/0673 ,  H01L21/30608 ,  H01L21/3083 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

公开(公告)号：US09466717B1

公开(公告)日：2016-10-11

申请号：US14680172

申请日：2015-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/82 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78639 ,  H01L29/78654

Abstract: The present disclosure provides, in a first aspect, a semiconductor device including an SOI substrate portion, a gate structure formed on the SOI substrate portion and source and drain regions having respective source and drain height levels, wherein the source and drain height levels are different. The semiconductor device may be formed by forming a gate structure over an SOI substrate portion, recessing the SOI substrate portion at one side of the gate structure so as to form a trench adjacent to the gate structure and forming source and drain regions at opposing sides of the gate structure, one of the source and drain regions being formed in the trench.

Abstract translation: 本公开在第一方面提供了一种半导体器件，其包括SOI衬底部分，形成在SOI衬底部分上的栅极结构以及具有各自的源极和漏极高度水平的源极和漏极区域，其中源极和漏极高度水平是不同的 。 可以通过在SOI衬底部分上形成栅极结构来形成半导体器件，在栅极结构的一侧凹入SOI衬底部分，以形成与栅极结构相邻的沟槽，并在栅极结构的相对侧形成源极和漏极区域 栅极结构，其中一个源极和漏极区域形成在沟槽中。

公开(公告)号：US09263270B2

公开(公告)日：2016-02-16

申请号：US13911857

申请日：2013-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ran Yan ,  Nicolas Sassiat ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/4763 ,  H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/265 ,  H01L21/2658 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract translation: 在先进技术节点上形成半导体器件结构的方法和相应的半导体器件结构在低于100nm的技术节点上提供。 在一些说明性实施例中，在将栅极电介质层结构和用于形成栅极结构的多晶硅层图案化并且将源极和漏极区域注入到其中之前，至少将至少注入形成在电介质层结构上的多晶硅层中的氟注入工艺 门结构的两侧。

公开(公告)号：US20150287782A1

公开(公告)日：2015-10-08

申请号：US14246983

申请日：2014-04-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Nicolas Sassiat ,  Ran Yan ,  Kun-Hsien Lin ,  Jan Hoentschel

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/30608 ,  H01L21/3083 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method includes providing a semiconductor substrate, defining a length on the semiconductor substrate corresponding to opposing vertices of a nanowire, removing a portion of the semiconductor substrate to provide a first fin structure and a second fin structure, etching a first cavity proximate to the first side, depositing a protective layer in the first cavity, removing a portion of the protective layer to expose a portion of the semiconductor substrate, and etching a second cavity at the exposed semiconductor substrate where the first and second cavities communicate. The first and second fin structures are adjacent where the length of the first fin structure corresponds to the opposing vertices and has a first side and a second side.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种方法包括提供半导体衬底，在半导体衬底上限定对应于纳米线的相对顶点的长度，去除半导体衬底的一部分以提供第一鳍结构和第二鳍结构，蚀刻第一腔 在所述第一侧附近沉积保护层，去除所述保护层的一部分以暴露所述半导体衬底的一部分，以及蚀刻所述第一和第二腔连通的所述暴露的半导体衬底处的第二腔。 第一鳍片结构和第二鳍片结构相邻，其中第一鳍片结构的长度对应于相对的顶点，并且具有第一侧面和第二侧面。

公开(公告)号：US20150287646A1

公开(公告)日：2015-10-08

申请号：US14244651

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L29/167 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供在半导体衬底上形成的具有n沟道栅极叠层和p沟道栅叠层的结构。 该方法包括在邻近p沟道栅极叠层的半导体衬底中形成卤素注入区，并在邻近p沟道栅叠层的半导体衬底中形成延伸注入区。 该方法还包括通过执行激光退火工艺来退火邻近p沟道栅叠层的半导体衬底中的卤注入区和延伸注入区。 此外，该方法在邻近n沟道栅叠层的半导体衬底中形成延伸注入区。

公开(公告)号：US20150014777A1

公开(公告)日：2015-01-15

申请号：US13942034

申请日：2013-07-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Joerg Schoenekess ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/66477

Abstract: The present disclosure provides an improved method for forming a thin semiconductor alloy layer on top of a semiconductor layer. The proposed method relies on an implantation of appropriate impurity species before performing deposition of the semiconductor alloy film. The implanted species cause the semiconductor alloy layer to be less unstable to wet and dry etches performed on the device surface after deposition. Thus, the thickness uniformity of the semiconductor alloy film may be substantially increased if the film is deposited after performing the implantation. On the other hand, some implanted impurities have been found to decrease the growth rate of the semiconductor alloy layer. Thus, by selectively implanting appropriate impurities in predetermined portions of a wafer, a single deposition step may be used in order to form a semiconductor alloy layer with a thickness which may be locally adjusted at will.

Abstract translation: 本公开提供了一种用于在半导体层的顶部上形成薄半导体合金层的改进方法。 所提出的方法依赖于在进行半导体合金膜的沉积之前植入适当的杂质物质。 植入的物质导致半导体合金层在沉积后在器件表面上进行的湿法干蚀刻不太稳定。 因此，如果在进行植入之后沉积膜，则半导体合金膜的厚度均匀性可以显着增加。 另一方面，已经发现一些植入的杂质降低了半导体合金层的生长速率。 因此，通过在晶片的预定部分选择性地注入合适的杂质，可以使用单个沉积步骤以形成可以随意地局部调整的厚度的半导体合金层。

公开(公告)号：US20140264626A1

公开(公告)日：2014-09-18

申请号：US14174474

申请日：2014-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Alban Zaka ,  Nicolas Sassiat ,  Jan Hoentschel ,  Martin Trentzsch ,  Carsten Grass

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/7833

Abstract: The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer.

Abstract translation: 在一些方面，本公开提供了一种用于半导体器件的栅电极结构。 在本文的一些说明性实施例中，栅电极结构包括在半导体衬底的第一有源区上的第一高k电介质层和第一高k电介质层上的第二高k电介质层。 第一高k电介质层具有并入其中的金属物质，用于调节第一高k电介质层的功函数。

公开(公告)号：US20140256097A1

公开(公告)日：2014-09-11

申请号：US13785557

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Jan Hoentschel ,  Torben Balzer

IPC: H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for forming a semiconductor device is provided which includes providing a gate structure in an active region of a semiconductor substrate, wherein the gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to the gate structure and, thereafter, performing a fluorine implantation process. Also a method for forming a CMOS integrated circuit structure is provided which includes providing a semiconductor substrate with a first active region and a second active region, forming a first gate structure in the first active region and a second gate structure in the second active region, wherein each gate structure includes a gate insulating layer having a high-k material, a gate metal layer and a gate electrode layer, forming sidewall spacers adjacent to each of the first and second gate structures and, thereafter, performing a fluorine implantation process.

Abstract translation: 提供了一种用于形成半导体器件的方法，其包括在半导体衬底的有源区域中提供栅极结构，其中所述栅极结构包括具有高k材料，栅极金属层和栅极电极层的栅极绝缘层， 形成与栅极结构相邻的侧壁间隔，之后进行氟注入工艺。 还提供了一种用于形成CMOS集成电路结构的方法，其包括提供具有第一有源区和第二有源区的半导体衬底，在第一有源区中形成第一栅极结构，在第二有源区中形成第二栅极结构， 其中每个栅极结构包括具有高k材料，栅极金属层和栅极电极层的栅极绝缘层，形成与第一和第二栅极结构中的每一个相邻的侧壁间隔，之后执行氟注入工艺。