公开(公告)号：US09672313B2

公开(公告)日：2017-06-06

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Yuping Ren ,  Chin Teong Lim ,  Xusheng Wu ,  Paul Ackmann

IPC: G06F17/50 ,  H01L23/522 ,  H01L27/02

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US09496280B1

公开(公告)日：2016-11-15

申请号：US14700748

申请日：2015-04-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Bingwu Liu ,  Xusheng Wu

IPC: H01L21/76 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/73 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/0684 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/0623 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/66568 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/78

Abstract: A method can include epitaxially growing epitaxial growth material within a logic region of a semiconductor structure. A method can include performing simultaneously with the growing epitaxial growth within an analog region of the semiconductor structure. A method can include performing epitaxial growth to form an epitaxial growth formation that defines an electrode of an analog device within an analog region of the semiconductor structure, wherein the performing includes using a first surface and a second surface as seed surfaces.

Abstract translation: 一种方法可以包括在半导体结构的逻辑区域内外延生长外延生长材料。 一种方法可以包括与半导体结构的模拟区域内的增长的外延生长同时执行。 一种方法可以包括进行外延生长以形成限定半导体结构的模拟区域内的模拟器件的电极的外延生长结构，其中执行包括使用第一表面和第二表面作为晶种表面。

公开(公告)号：US09431424B1

公开(公告)日：2016-08-30

申请号：US14872294

申请日：2015-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu

IPC: H01L29/00 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L49/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/283 ,  H01L27/06 ,  H01L29/423 ,  H01L29/06 ,  H01L21/306

CPC classification number: H01L27/1203 ,  H01L21/28008 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/4232

Abstract: Fabricating FEOL metal gate resistor structures and the resulting device are disclosed. Embodiments include providing a Si layer-insulator layer-Si substrate stack; forming STI regions at first through fourth sides of a rectangular active-area of the Si layer, the first side opposing the third, the STI extending into the substrate; recessing the STI below the insulator upper surface; undercutting the active-area, forming channels in the insulator along and under perimeter edges of the active-area; conformally forming a high-k dielectric on all exposed surfaces; forming metal on the high-k dielectric and filling the channels; removing the metal except for the filled channels and a portion over each of the STI at the first and third sides and overlapping the active-area; and forming low-k spacers on exposed opposing sidewalls of the metal portions and exposed vertical surfaces of the high-k dielectric on edges of the active-area and the filled channels.

Abstract translation: 公开了制造FEOL金属栅极电阻器结构和所得到的器件。 实施例包括提供Si层 - 绝缘体层-Si衬底叠层; 在Si层的矩形有源区的第一至​​第四侧形成STI区，与第三相对的第一侧，STI延伸到衬底中; 将STI在绝缘体上表面下方凹入; 底切主动区域，在活动区域​​的周边边缘沿着或沿着绝缘体形成通道; 在所有暴露表面上共形形成高k电介质; 在高k电介质上形成金属并填充通道; 去除除了填充的通道之外的金属和在第一和第三侧上的每个STI上的部分，并与活动区域重叠; 以及在金属部分的暴露的相对的侧壁上和在有源区域和填充的通道的边缘上的高k电介质的暴露的垂直表面上形成低k隔离物。

公开(公告)号：US20160049468A1

公开(公告)日：2016-02-18

申请号：US14823319

申请日：2015-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Wanxun He ,  Hongliang Shen

IPC: H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0646 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit product is disclosed that includes a plurality of trenches in a semiconducting substrate that define first, second and third fins, wherein the fins are side-by-side, and wherein the second fin is positioned between the first and third fins, a layer of insulating material in the plurality of trenches such that a desired height of the first, second and third fins is positioned above an upper surface of the layer of insulating material, a recess defined in the second fin that at least partially defines a cavity in the layer of insulating material, an SDB isolation structure in the cavity on the recessed portion of the second fin, wherein the SDB isolation structure has an upper surface that is above the upper surface of the layer of insulating material, and a gate structure for a transistor positioned above the SDB isolation structure.

Abstract translation: 公开了一种集成电路产品，其包括限定第一，第二和第三鳍片的半导体衬底中的多个沟槽，其中散热片并排，并且其中第二鳍片位于第一和第三鳍片之间， 多个沟槽中的绝缘材料层，使得第一，第二和第三鳍片的期望高度位于绝缘材料层的上表面上方，限定在第二鳍片中的凹部，其至少部分地限定在第 所述绝缘材料层，在所述第二鳍片的凹陷部分上的空腔中的SDB隔离结构，其中所述SDB隔离结构具有位于所述绝缘材料层的上表面上方的上表面，以及用于 晶体管位于SDB隔离结构之上。

公开(公告)号：US20150380515A1

公开(公告)日：2015-12-31

申请号：US14319462

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Xusheng Wu ,  Hong Yu ,  Zhao Lun

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.

Abstract translation: 提供了用于形成外延（epi）源极/漏极（S / D）和/或具有外延S / D的半导体器件的方法。 在本发明的实施例中，epi S / D的第一部分形成在鳍状衬底中的翅片上的S / D区域中。 在形成第一部分之后，但在形成S / D之前，在S / D区域中形成二次间隔物。 然后，在S / D区域中形成S / D的剩余部分。 结果，S / D通过辅助间隔件与栅极堆叠分离。

公开(公告)号：US09171752B1

公开(公告)日：2015-10-27

申请号：US14457325

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Changyong Xiao ,  Wanxun He ,  Hongliang Shen

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/0646 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653

Abstract: One illustrative method disclosed herein includes, among other things, forming first, second and third fins that are arranged side-by-side, forming a recessed layer of insulating material in a plurality of trenches, after recessing the layer of insulating material, masking the first and second fins while exposing a portion of the axial length of the second fin, removing the exposed portion of the second fin so as to thereby define a cavity in the recessed layer of insulating material, forming an SDB isolation structure in the cavity, wherein the SDB isolation structure has an upper surface that is positioned above the recessed upper surface of the recessed layer of insulating material, removing the masking layer, and forming a gate structure for a transistor above the SDB isolation structure.

Abstract translation: 本文公开的一种说明性方法包括形成并排布置的第一，第二和第三鳍片，在凹陷绝缘材料层之后，在多个沟槽中形成绝缘材料的凹陷层，掩蔽 第一和第二鳍片，同时暴露第二鳍片的轴向长度的一部分，去除第二鳍片的暴露部分，从而在绝缘材料的凹陷层中限定空腔，在空腔中形成SDB隔离结构，其中 SDB隔离结构具有位于绝缘材料的凹陷层的凹陷的上表面上方的上表面，去除掩模层，并且在SDB隔离结构之上形成用于晶体管的栅极结构。

公开(公告)号：US10586860B2

公开(公告)日：2020-03-10

申请号：US15970217

申请日：2018-05-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Laertis Economikos ,  Xusheng Wu ,  John Zhang ,  Haigou Huang ,  Hui Zhan ,  Tao Han ,  Haiting Wang ,  Jinping Liu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/3065

Abstract: In conjunction with a replacement metal gate (RMG) process for forming a fin field effect transistor (FinFET), gate isolation methods and associated structures leverage the formation of distinct narrow and wide gate cut regions in a sacrificial gate. The formation of a narrow gate cut between closely-spaced fins can decrease the extent of etch damage to interlayer dielectric layers located adjacent to the narrow gate cut by delaying the deposition of such dielectric layers until after formation of the narrow gate cut opening. The methods and resulting structures also decrease the propensity for short circuits between later-formed, adjacent gates.

公开(公告)号：US10510613B2

公开(公告)日：2019-12-17

申请号：US15878081

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

IPC: H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/28

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

公开(公告)号：US20190280114A1

公开(公告)日：2019-09-12

申请号：US15919079

申请日：2018-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng Gao ,  Daniel Jaeger ,  Michael Aquilino ,  Patrick Carpenter ,  Xusheng Wu ,  Haigou Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.

公开(公告)号：US10347740B2

公开(公告)日：2019-07-09

申请号：US15367366

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Min-hwa Chi ,  Edmund Kenneth Banghart

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.