公开(公告)号：US20160190292A1

公开(公告)日：2016-06-30

申请号：US15061725

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： James W. Adkisson ,  David L. Harame ,  Michael L. Kerbaugh ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/732 ,  H01L29/10 ,  H01L29/737 ,  H01L29/161 ,  H01L29/45 ,  H01L29/08 ,  H01L29/06 ,  H01L29/04

CPC classification number: H01L29/732 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/45 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7327 ,  H01L29/7371 ,  H01L29/7378

Abstract: The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.

公开(公告)号：US09318584B2

公开(公告)日：2016-04-19

申请号：US14492582

申请日：2014-09-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Robert K. Leidy ,  Qizhi Liu

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L21/762

CPC classification number: H01L29/732 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 器件结构包括衬底中的集电极区域，延伸到衬底中并由电绝缘体构成的多个隔离结构以及衬底中的隔离区域。 隔离结构具有长度并且以横向于长度的间距布置，使得每个相邻的一对隔离结构被基板的相应部分分开。 隔离区域通过集电区域的第一部分与隔离结构中的至少一个横向分离。 隔离区域将收集区域的第二部分与收集器区域的第一部分横向分离。 器件结构还包括在集电极区域的第二部分上的本征基极和在本征基极上的发射极。 发射极相对于隔离结构的长度具有横向定向的长度。

公开(公告)号：US09276093B2

公开(公告)日：2016-03-01

申请号：US14522090

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Margaret A. Faucher ,  Paula M. Fisher ,  Thomas H. Gabert ,  Joseph P. Hasselbach ,  Qizhi Liu ,  Glenn C. MacDougall

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/737 ,  H01L21/762

CPC classification number: H01L29/732 ,  H01L21/76221 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/737 ,  H01L29/7371

Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.

公开(公告)号：US09236499B2

公开(公告)日：2016-01-12

申请号：US14496285

申请日：2014-09-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kevin K. Chan ,  John J. Ellis-Monaghan ,  David L. Harame ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/808 ,  H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  H01L27/06 ,  G06F17/50 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/8086 ,  G06F17/5045 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/1058 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/732 ,  H01L29/7375 ,  H01L29/808

Abstract: Junction field-effect transistors and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate.

Abstract translation: 结场效应晶体管和结型场效应晶体管的设计结构。 结场效应晶体管的源极和漏极由通过选择性外延生长并与半导体层的顶表面直接接触的半导体材料组成。 形成与在源极和漏极之间横向设置在半导体层中的沟道对准的栅极。 源极，漏极和半导体层各自包括与包括栅极的第一半导体材料具有相反导电类型的第二半导体材料。

公开(公告)号：US09231087B2

公开(公告)日：2016-01-05

申请号：US14677303

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Benoit ,  James R. Elliott ,  Peter B. Gray ,  Alvin J. Joseph ,  Qizhi Liu ,  Christa R. Willets

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/06 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

公开(公告)号：US10971597B2

公开(公告)日：2021-04-06

申请号：US16551061

申请日：2019-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/165 ,  H01L29/737

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

公开(公告)号：US10833153B2

公开(公告)日：2020-11-10

申请号：US15703220

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qizhi Liu ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L21/84 ,  H01L21/764 ,  H01L21/762 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.

公开(公告)号：US10818772B2

公开(公告)日：2020-10-27

申请号：US15961364

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Pernell Dongmo ,  Cameron Luce ,  James W. Adkisson ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

公开(公告)号：US10777668B2

公开(公告)日：2020-09-15

申请号：US16106344

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/06

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.

公开(公告)号：US20190035919A1

公开(公告)日：2019-01-31

申请号：US15664418

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L23/535 ,  H01L29/165 ,  H01L21/84 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/7378 ,  H01L21/02532 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.