公开(公告)号：US10002793B1

公开(公告)日：2018-06-19

申请号：US15464591

申请日：2017-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  David P. Brunco ,  Jinping Liu ,  Baofu Zhu ,  Shesh Mani Pandey

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/225

CPC classification number: H01L21/2254 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823892

Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.

公开(公告)号：US20170288041A1

公开(公告)日：2017-10-05

申请号：US15091256

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Baofu Zhu ,  Francis Benistant

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/0217 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method includes forming a fin in a semiconductor substrate. An isolation structure is formed adjacent the fin. A first portion of the fin extends above the isolation structure. A gate electrode is formed above the first portion of the fin. A fin spacer is formed on the first portion of the fin. The fin spacer covers less than 50% of a height of the first portion of the fin. An implantation process is performed in the presence of the fin spacer to form a doped region in the first portion of the fin.

公开(公告)号：US20170200674A1

公开(公告)日：2017-07-13

申请号：US14993238

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar Singh ,  Shesh Mani Pandey

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/321 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: Methodologies and a device for reducing capacitance and improving profile control are provided. Embodiments include forming metal vias in a first dielectric layer; forming a graded interlayer dielectric over the metal vias; forming a metal layer in the graded ILD over one of the metal vias; and forming a hydrogenated amorphous silicon carbon film over the metal layer.

公开(公告)号：US10825910B1

公开(公告)日：2020-11-03

申请号：US16386545

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Shesh Mani Pandey

IPC: H01L29/82 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768

Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

公开(公告)号：US10586736B2

公开(公告)日：2020-03-10

申请号：US16005073

申请日：2018-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Ruilong Xie ,  Shesh Mani Pandey ,  Hui Zang ,  Garo Jacques Derderian ,  Scott Beasor

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L21/308 ,  H01L21/762

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a hybrid fin cut with improved fin profiles and methods of manufacture. The structure includes: a plurality of fin structures in a first region of a first density of fin structures; a plurality of fin structures in a second region of a second density of fin structures; and a plurality of fin structures in a third region of a third density of fin structures. The first density, second density and third density of fin structures are different densities of fin structures, and the plurality of fin structures in the first region, the second region and the third region have a substantially uniform profile.

公开(公告)号：US20180286946A1

公开(公告)日：2018-10-04

申请号：US15967156

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shesh Mani Pandey

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A shallow trench isolation (STI) structure is formed having a conventional STI trench structure formed of dielectric material extending into the substrate. A planarizing stack of nitride and oxide is formed above the STI trench structure (and optionally a dummy gate may be formed above this stack). After further conventional processing, the nitride layer results in a structure that extends laterally outward beyond the outer edges of the underlying STI structure—creating a shadow or umbrella structure. The S/D cavity is formed (between the active gate and dummy gate) and the epitaxial S/D regions are grown. The placement and configuration of the nitride layer assists in reducing the amount of substrate material removed adjacent the STI structure during the S/D region cavity formation.

公开(公告)号：US10084093B1

公开(公告)日：2018-09-25

申请号：US15600872

申请日：2017-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shiv Kumar Mishra ,  Sunil Kumar Singh ,  Shesh Mani Pandey

IPC: H01L21/00 ,  H01L29/78 ,  H01L23/532 ,  H01L29/66 ,  H01L29/49

Abstract: During formation of a trench silicide contact, a sacrificial layer is incorporated into the trench directly over source/drain junctions prior to metallization of the trench. Selective removal of the sacrificial layer widens the trench proximate to the source/drain junctions, increasing the contact area and correspondingly decreasing the contact resistance between the source/drain junctions and a silicide layer.

公开(公告)号：US10056486B2

公开(公告)日：2018-08-21

申请号：US15079142

申请日：2016-03-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Pei Zhao ,  Zhenyu Hu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.

公开(公告)号：US09966433B2

公开(公告)日：2018-05-08

申请号：US15227330

申请日：2016-08-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiqing Li ,  Shesh Mani Pandey ,  Francis Benistant

IPC: H01L29/08 ,  H01L21/22 ,  H01L29/167 ,  H01L29/16 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/2225 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming NFET S/D structures with multiple layers, with consecutive epi-SiP layers being doped at increasing dosages of P and the resulting device are provided. Embodiments include forming multiple epi-Si layers in each S/D cavity of a NFET; and performing in-situ doping of P for each epi-Si layer, wherein consecutive epi-Si layers are doped at increasing dosages of P.

公开(公告)号：US09947788B2

公开(公告)日：2018-04-17

申请号：US15019273

申请日：2016-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shesh Mani Pandey ,  Pei Zhao ,  Baofu Zhu ,  Francis L. Benistant

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.