Multiple-time programmable (MTP) memory device with a wrap-around control gate

    公开(公告)号:US10886287B2

    公开(公告)日:2021-01-05

    申请号:US16246639

    申请日:2019-01-14

    摘要: One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.

    Interconnect structures with reduced capacitance

    公开(公告)号:US10672710B2

    公开(公告)日:2020-06-02

    申请号:US16000174

    申请日:2018-06-05

    摘要: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.

    DUAL DEVELOPING METHODS FOR LITHOGRAPHY PATTERNING

    公开(公告)号:US20190079408A1

    公开(公告)日:2019-03-14

    申请号:US15698775

    申请日:2017-09-08

    IPC分类号: G03F7/32

    摘要: The disclosure is directed to a method for lithographic patterning. The method may include: exposing a photoresist to a radiant energy; developing the photoresist in a first developer, thereby creating an opening within the photoresist including sidewalls having a slant; and developing the photoresist in a second developer immediately after the developing of the photoresist in the first developer, thereby reducing the slant of the sidewalls of the opening. Where the photoresist is a positive tone development (PTD) photoresist, the first developer may include a positive developer, and the second developer may include a negative developer. Where the photoresist is a negative tone development (NTD) photoresist, the first developer may include a negative developer, and the second developer may include a positive developer.

    MULTIPLE-TIME PROGRAMMABLE (MTP) MEMORY DEVICE WITH A WRAP-AROUND CONTROL GATE

    公开(公告)号:US20200227424A1

    公开(公告)日:2020-07-16

    申请号:US16246639

    申请日:2019-01-14

    摘要: One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.