公开(公告)号：US20150279973A1

公开(公告)日：2015-10-01

申请号：US14242472

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/84

CPC classification number: H01L29/66795 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.

Abstract translation: 本文公开的一种说明性方法包括进行外延沉积工艺以在绝缘材料的凹陷层上方和鳍的暴露部分上形成外延SiGe层，其中外延硅 - 锗（SixGe1-x）等于或大于用于最终翅片的锗的目标浓度，在惰性处理环境中进行热退火工艺以使外延SiGe中的锗扩散到翅片中，从而限定SiGe区域 在翅片中，在进行热退火处理之后，进行至少一个处理操作以去除外延SiGe，并且在去除外延SiGe之后，在SiGe区域的至少一部分周围形成栅极结构。

公开(公告)号：US20140273423A1

公开(公告)日：2014-09-18

申请号：US13798616

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jody A. Fronheiser ,  Jeremy A. Wahl ,  Kerem Akarvardar ,  Ajey P. Jacob ,  Daniel T. Pham

IPC: H01L29/66

CPC classification number: H01L29/42392 ,  B82Y40/00 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Abstract translation: 本文公开的一种方法包括在半导体衬底上形成具有至少30％的锗浓度的硅/锗层，形成多个间隔开的沟槽，其延伸穿过硅/锗层并且至少部分地进入半导体 衬底，其中所述沟槽限定由所述衬底的一部分和所述硅/锗层的一部分组成的器件的鳍结构，所述硅/锗层的所述部分具有第一横截面构造，形成层 的绝缘材料在沟槽中并在鳍结构之上，对器件进行退火处理，以使硅/锗层的第一截面构型变为不同于第二截面结构 第一横截面构造，以及围绕具有第二横截面的硅/锗层的至少一部分形成最终栅极结构 功能配置

公开(公告)号：US10163677B2

公开(公告)日：2018-12-25

申请号：US15848371

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

公开(公告)号：US10026659B2

公开(公告)日：2018-07-17

申请号：US14608815

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/02

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.

公开(公告)号：US09881830B2

公开(公告)日：2018-01-30

申请号：US14590591

申请日：2015-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L21/76202 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.

公开(公告)号：US09455140B2

公开(公告)日：2016-09-27

申请号：US14525351

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jody A. Fronheiser ,  Murat Kerem Akarvardar

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/78 ,  H01L21/18

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02579 ,  H01L21/02664 ,  H01L21/18 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract translation: 本文中公开的一种说明性方法包括进行第一和第二原位掺杂，外延沉积工艺以分别在半导体衬底之上形成第一和第二层原位掺杂的外延半导体材料，其中第一和第二 层具有高水平的锗和低水平的P型掺杂剂材料，并且第一和第二层中的另一层具有低水平的锗和高水平的P型掺杂剂材料，并且进行混合热退火工艺 在第一和第二层上形成具有高水平的锗和高水平的P型掺杂剂材料的最终硅锗材料。

公开(公告)号：US20160268399A1

公开(公告)日：2016-09-15

申请号：US14643409

申请日：2015-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Steven Bentley

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31051 ,  H01L21/31111 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a layer of insulating material in the source/drain regions of the device, wherein the layer of insulating material has an upper surface that is substantially planar with an upper surface of a gate cap layer, recessing the layer of insulating material such that its recessed upper surface exposes a surface of the fin, performing another etching process to remove at least a portion of the fin and thereby define a recessed fin trench positioned above the recessed fin, and forming an epitaxial semiconductor material that is at least partially positioned in the recessed fin trench.

Abstract translation: 本文公开的一种说明性方法包括在器件的源极/漏极区域中形成绝缘材料层，其中绝缘材料层具有与栅极盖层的上表面基本上平面的上表面 使绝缘材料层凹陷，使得其凹陷的上表面暴露在鳍片的表面上，执行另一蚀刻工艺以移除鳍片的至少一部分，从而限定位于凹鳍片上方的凹陷散热片沟槽，并形成外延 所述半导体材料至少部分地位于所述凹陷散热片沟槽中。

公开(公告)号：US09337022B1

公开(公告)日：2016-05-10

申请号：US14742471

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Bruce Doris

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/304 ,  H01L29/165

CPC classification number: H01L21/0245 ,  H01L21/02496 ,  H01L21/0251 ,  H01L21/02551 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of creating a virtual relaxed substrate includes providing a bulk semiconductor substrate, and creating a layer of strained semiconductor material on the substrate, a non-zero lattice mismatch of less than about 2% being present between the substrate and the layer of strained semiconductor material, and the layer of strained semiconductor material having a thickness of from about 50 nm to about 150 nm. The method further includes etching through the layer of strained semiconductor material and into the substrate to create shaped pillars separated by slits and sized to achieve edge effect relaxation throughout each shaped pillar, merging a top portion of the pillars with single crystal growth of epitaxial material to create a continuous surface while substantially maintaining the slits, and creating a virtual relaxed substrate by creating a layer of epitaxial composite semiconductor material over the continuous surface.

Abstract translation: 创建虚拟松弛衬底的方法包括提供体半导体衬底，以及在衬底上产生应变半导体材料层，小于约2％的非零晶格失配存在于衬底和应变半导体层之间 材料和具有约50nm至约150nm厚度的应变半导体材料层。 该方法还包括蚀刻通过应变半导体材料层并进入衬底以产生由狭缝分开的成形柱，并且尺寸设计成实现每个成形柱的边缘效应松弛，将柱的顶部部分与外延材料的单晶生长合并成 创建连续的表面，同时基本上保持狭缝，并通过在连续表面上形成外延复合半导体材料层来产生虚拟的松弛衬底。

公开(公告)号：US09245980B2

公开(公告)日：2016-01-26

申请号：US14242472

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Ajey Poovannummoottil Jacob

IPC: H01L29/66 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/1054

Abstract: One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.

Abstract translation: 本文公开的一种说明性方法包括进行外延沉积工艺以在绝缘材料的凹陷层上方和鳍的暴露部分上形成外延SiGe层，其中外延硅 - 锗（SixGe1-x）等于或大于用于最终翅片的锗的目标浓度，在惰性处理环境中进行热退火工艺以使外延SiGe中的锗扩散到翅片中，从而限定SiGe区域 在翅片中，在进行热退火处理之后，进行至少一个处理操作以去除外延SiGe，并且在去除外延SiGe之后，在SiGe区域的至少一部分周围形成栅极结构。

公开(公告)号：US09117875B2

公开(公告)日：2015-08-25

申请号：US14155499

申请日：2014-01-15

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Bruce Doris ,  Kern Rim

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/324

CPC classification number: H01L21/76224 ,  H01L21/02532 ,  H01L21/3083 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: Forming a plurality of initial trenches that extend through a layer of silicon-germanium and into a substrate to define an initial fin structure comprised of a portion of the layer of germanium-containing material and a first portion of the substrate, forming sidewall spacers adjacent the initial fin structure, performing an etching process to extend the initial depth of the initial trenches, thereby forming a plurality of final trenches having a final depth that is greater than the initial depth and defining a second portion of the substrate positioned under the first portion of the substrate, forming a layer of insulating material over-filling the final trenches and performing a thermal anneal process to convert at least a portion of the first or second portions of the substrate into a silicon dioxide isolation material that extends laterally under an entire width of the portion of the germanium-containing material.

Abstract translation: 形成多个初始沟槽，其延伸穿过硅 - 锗层并进入衬底以限定由锗含量材料层的一部分和衬底的第一部分组成的初始鳍结构，形成邻近 初始鳍结构，执行蚀刻处理以延长初始沟槽的初始深度，由此形成多个最终深度大于初始深度的最终沟槽，并且限定位于第一部分第一部分下方的衬底的第二部分 所述衬底形成覆盖所述最终沟槽的绝缘材料层，并执行热退火工艺，以将所述衬底的所述第一或第二部分的至少一部分转化成二氧化硅隔离材料，所述二氧化硅隔离材料横向延伸在整个宽度 含锗材料的一部分。