公开(公告)号：US20160293756A1

公开(公告)日：2016-10-06

申请号：US14675298

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/78 ,  H01L29/267 ,  H01L29/165 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/785

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

Abstract translation: 使用FinFET器件架构，在硅中实现隧道晶体管。 隧道FinFET具有非平面的垂直结构，其从形成在硅衬底中的掺杂漏极的表面延伸出来。 垂直结构包括由减法蚀刻工艺限定的轻掺杂的鳍，以及通过外延生长形成在鳍的顶部上的重掺杂源。 漏极和沟道具有相似的极性，与源极相反。 栅极邻接通道区域，电容地控制从相对侧通过通道的电流。 源极，漏极和栅极端子都可以通过在器件完成之后形成的前侧触点电可访问。 隧道FinFET的制造与常规CMOS制造工艺兼容，包括替换金属栅极和自对准接触工艺。 与传统的平面器件相比，低功耗操作允许隧道FinFET提供高电流密度。

公开(公告)号：US20160293371A1

公开(公告)日：2016-10-06

申请号：US14675359

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01H59/00 ,  H01H11/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US20160043177A1

公开(公告)日：2016-02-11

申请号：US14456272

申请日：2014-08-11

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Tenko YAMASHITA ,  Chun-chen YEH ,  Veeraraghavan S. BASKER

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/1037 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.

Abstract translation: 制造半导体器件的方法可以包括在绝缘层上形成半导体层之上的虚拟栅极，在半导体层上方形成侧壁间隔，在虚设栅极的相对侧上，在侧壁间隔物的相对侧上形成源极和漏极区域 并且在侧壁间隔物之间​​移除半导体层的虚拟栅极和下面的部分，以提供厚度小于稀薄沟道区域外的半导体层的剩余部分的薄化沟道区域。 该方法还可以包括在稀疏的沟道区域和侧壁间隔物之间​​形成替代栅极堆叠，并且具有在侧壁间隔物的相邻底部的水平面下方延伸的下部。

公开(公告)号：US20160380118A1

公开(公告)日：2016-12-29

申请号：US15260206

申请日：2016-09-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing LIU ,  John H. ZHANG

IPC: H01L29/84 ,  H01L21/306 ,  H01L21/02 ,  H01H49/00 ,  H01H59/00

CPC classification number: H01L29/84 ,  B82B3/00 ,  H01H1/0094 ,  H01H49/00 ,  H01H50/005 ,  H01H59/0009 ,  H01H2001/0084 ,  H01L21/02532 ,  H01L21/30608

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

Abstract translation: 纳米级机电开关形式的集成晶体管消除了CMOS电流泄漏并提高了开关速度。 纳米尺度的机电开关具有从衬底的一部分延伸到空腔中的半导体悬臂。 悬臂响应于施加到晶体管栅极的电压而弯曲，从而在栅极下形成导电沟道。 当设备关闭时，悬臂返回到其静止位置。 悬臂的这种运动打破了电路，恢复了阻挡电流的门下方的空隙，从而解决了泄漏问题。 纳米机电开关的制造与现有的CMOS晶体管制造工艺兼容。 通过掺杂悬臂并使用背偏压和金属悬臂尖，可以进一步提高开关的灵敏度。 纳米机电开关的占地面积可以小至0.1×0.1μm2。

公开(公告)号：US20160190315A1

公开(公告)日：2016-06-30

申请号：US14587849

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing LIU ,  Thomas SKOTNICKI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

公开(公告)号：US20160190303A1

公开(公告)日：2016-06-30

申请号：US14588116

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Hong HE ,  Bruce DORIS

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/12 ,  H01L21/762 ,  H01L21/02 ,  H01L21/225 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

Abstract translation: 制造结构稳定的绝缘体上的FinFET的方法使用氮化硅衬垫来防止在SiGe鳍的基底处的去稳定化氧化。 氮化硅衬垫阻止氧气进入翅片的下角，以便制造高浓度SiGe翅片。 氮化硅衬垫即使其厚度小于约5nm也是有效的。 使用SiN衬垫为具有较高锗含量，在25-55％锗浓度范围内的翅片提供结构稳定性。

公开(公告)号：US20160035843A1

公开(公告)日：2016-02-04

申请号：US14782190

申请日：2013-04-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERIGES ALTERNATIVES ,  STMICROELECTRONICS INC

Inventor： Maud VINET ,  Laurent GRENOUILLET ,  Qing LIU

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/06 ,  H01L21/32 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L21/31133 ,  H01L21/32 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/6656

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

Abstract translation: 一种用于制造具有不同类型的具有升高的源极和漏极区域以及不同重叠区域的晶体管的微电子器件的方法。