公开(公告)号：US12176023B2

公开(公告)日：2024-12-24

申请号：US18080456

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Venkatesh P. Gopinath ,  Navneet Jain ,  Bipul C. Paul ,  Halid Mulaosmanovic

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H01L21/28 ,  H10B10/00

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

公开(公告)号：US20240377954A1

公开(公告)日：2024-11-14

申请号：US18315696

申请日：2023-05-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shashank NEMAWARKAR ,  Bipul C. Paul

IPC: G06F3/06

Abstract: An apparatus and method for providing high throughput memory responses are provided. The apparatus includes a memory device including a plurality of memory arrays, a memory controller configured to control the memory device, the memory controller having a read queue, a write queue, and an address match circuit, and a data output circuit. The memory controller receives a read request, searches the write queue for a write address that matches a read address of the read request, and sends data associated with the write address from the write queue to the data output circuit without accessing the memory device when the write address matches the read address, the write address that matches the read address being a target address. The data output circuit outputs the data associated with the target address to an external device.

公开(公告)号：US11776606B2

公开(公告)日：2023-10-03

申请号：US17365481

申请日：2021-07-01

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Amogh Agrawal ,  Ajey Poovannummoottil Jacob ,  Bipul C. Paul

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1697

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

公开(公告)号：US20230253017A1

公开(公告)日：2023-08-10

申请号：US17668962

申请日：2022-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ming YIN ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

公开(公告)号：US11075247B2

公开(公告)日：2021-07-27

申请号：US16691694

申请日：2019-11-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joe A. Versaggi

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.

公开(公告)号：US20210142850A1

公开(公告)日：2021-05-13

申请号：US16677790

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Steven R. Soss ,  Bipul C. Paul

IPC: G11C13/00 ,  H01L27/24

Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

公开(公告)号：US11004491B2

公开(公告)日：2021-05-11

申请号：US16582474

申请日：2019-09-25

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anuj Gupta ,  Bipul C. Paul ,  Joseph Versaggi

IPC: G11C5/06 ,  G11C11/16

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.

公开(公告)号：US10950610B2

公开(公告)日：2021-03-16

申请号：US16515913

申请日：2019-07-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Julien Frougier ,  Daniel Chanemougame ,  Hui Zang

IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L27/092

Abstract: Methods of forming a gate cut isolation for an SRAM include forming a first and second active nanostructures adjacent to each other and separated by a space; forming a sacrificial liner over at least a side of the first active nanostructure facing the space, causing a first distance between a remaining portion of the space and the first active nanostructure to be greater than a second distance between the remaining portion of the space and the second active nanostructure. A gate cut isolation is formed in the remaining portion of the space such that it is closer to the second active nanostructure than the first active nanostructure. The sacrificial liner is removed, and gates formed over the active nanostructures with the gates separated from each other by the gate cut isolation. An SRAM including the gate cut isolation and an IC structure including the SRAM are also included.