公开(公告)号：US11728348B2

公开(公告)日：2023-08-15

申请号：US17498241

申请日：2021-10-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli ,  Michel J. Abou-Khalil

IPC: H01L23/31 ,  H01L27/12 ,  H01L27/02 ,  H01L29/16 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/40 ,  H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L21/84 ,  H01L21/3065 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/0207 ,  H01L29/0847 ,  H01L29/1087 ,  H01L29/16 ,  H01L29/401 ,  H01L29/41758 ,  H01L29/665

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked field effect transistors and methods of manufacture. The structure includes: at least one lower gate structure on a bottom of a trench formed in substrate material; insulator material partially filling trench and over the at least one lower gate structure; an epitaxial material on the insulator material and isolated from sidewalls of the trench; and at least one upper gate structure stacked vertically above the at least one lower gate structure and located on the epitaxial material.

公开(公告)号：US11637068B2

公开(公告)日：2023-04-25

申请号：US17121810

申请日：2020-12-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373 ,  H01L23/48 ,  H01L27/06

Abstract: Processing forms an integrated circuit structure having first and second layers on opposite sides of an insulator, and an interconnect structure extending through the insulator between the first layer and the second layer. The interconnect structure is formed in an opening extending through the insulator between the first layer and the second layer and has an electrical conductor in the opening extending between the first layer and the second layer and a thermally conductive electrical insulator liner along sidewalls of the opening extending between the first layer and the second layer. The electrical conductor is positioned to conduct electrical signals between the first layer and the second layer, and the thermally conductive electrical insulator liner is positioned to transfer heat between the first layer and the second layer.

公开(公告)号：US20230063731A1

公开(公告)日：2023-03-02

申请号：US17983436

申请日：2022-11-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US11574863B2

公开(公告)日：2023-02-07

申请号：US17169947

申请日：2021-02-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Venkata N. R. Vanukuru

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a device layer including a device on a substrate. A local interconnect layer is over the device layer, and includes a first dielectric material over the substrate. The first dielectric material has a first effective dielectric constant. A second dielectric material is over the device and adjacent the first dielectric material. The second dielectric material has a second effective dielectric constant less than the first effective dielectric constant.

公开(公告)号：US20220291126A1

公开(公告)日：2022-09-15

申请号：US17195887

申请日：2021-03-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik ,  Yusheng Bian

IPC: G01N21/64 ,  H01L31/12 ,  H01L31/02 ,  H01L31/0232 ,  G01N21/85

Abstract: A “lab on a chip” includes an optofluidic sensor and components to analyze signals from the optofluidic sensor. The optofluidic sensor includes a substrate, a channel at least partially defined by a portion of a layer of first material on the substrate, input and output fluid reservoirs in fluid communication with the channel, at least a first radiation source coupled to the substrate adapted to generate radiation in a direction toward the channel, and at least one photodiode positioned adjacent and below the channel.

公开(公告)号：US11444149B1

公开(公告)日：2022-09-13

申请号：US17182415

申请日：2021-02-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Yves T. Ngu ,  Mickey H. Yu

IPC: H01L27/12 ,  H01L27/06 ,  H01L49/02 ,  H01L27/08

Abstract: A resistor includes at least one polysilicon resistor element in a semiconductor substrate with each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor may include an insulator within a valley of the U-shape of each polysilicon resistor element. A plurality of polysilicon resistor elements can be sequentially interconnected to create a serpentine polysilicon resistor. The resistor may also include a dopant-including high resistivity (HR) polysilicon layer thereunder to provide electrical isolation from, and better thermal conduction to, for example, a base semiconductor substrate. The resistor can be used in an SOI substrate. A related method is also disclosed.

公开(公告)号：US20220221650A1

公开(公告)日：2022-07-14

申请号：US17146864

申请日：2021-01-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yusheng Bian ,  Roderick A. Augur ,  Kenneth J. Giewont ,  Karen Nummy ,  Edward Kiewra ,  Steven M. Shank

IPC: G02B6/122 ,  G02B6/136 ,  G02B6/34

Abstract: Structures including a grating coupler and methods of fabricating a structure including a grating coupler. The structure includes structure includes a dielectric layer on a substrate, a first waveguide core positioned in a first level over the dielectric layer, and a second waveguide core positioned in a second level over the dielectric layer. The second level differs in elevation above the dielectric layer from the first level. The first waveguide core includes a tapered section. The structure further includes a grating coupler having a plurality of segments positioned in the second level adjacent to the second waveguide core. The segments of the grating coupler and the tapered section of the first waveguide core are positioned in an overlapping arrangement.

公开(公告)号：US20220190108A1

公开(公告)日：2022-06-16

申请号：US17155469

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma B. Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Srikanth Srihari

IPC: H01L29/06 ,  H01L29/78

Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

公开(公告)号：US20220189877A1

公开(公告)日：2022-06-16

申请号：US17121810

申请日：2020-12-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L23/532 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/373

Abstract: Processing forms an integrated circuit structure having first and second layers on opposite sides of an insulator, and an interconnect structure extending through the insulator between the first layer and the second layer. The interconnect structure is formed in an opening extending through the insulator between the first layer and the second layer and has an electrical conductor in the opening extending between the first layer and the second layer and a thermally conductive electrical insulator liner along sidewalls of the opening extending between the first layer and the second layer. The electrical conductor is positioned to conduct electrical signals between the first layer and the second layer, and the thermally conductive electrical insulator liner is positioned to transfer heat between the first layer and the second layer.

公开(公告)号：US20220181361A1

公开(公告)日：2022-06-09

申请号：US17113418

申请日：2020-12-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy ,  Ramsey Hazbun

IPC: H01L27/144 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/18

Abstract: Structures including multiple photodiodes and methods of fabricating a structure including multiple photodiodes. A substrate has a first trench extending to a first depth into the substrate and a second trench extending to a second depth into the substrate that is greater than the first depth. A first photodiode includes a first light-absorbing layer containing a first material positioned in the first trench. A second photodiode includes a second light-absorbing layer containing a second material positioned in the second trench. The first material and the second material each include germanium.