公开(公告)号：US11333558B2

公开(公告)日：2022-05-17

申请号：US16181972

申请日：2018-11-06

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Pekarik ,  Steven M. Shank

IPC: G01K1/02 ,  H01L45/00 ,  G01K7/22 ,  H01L27/24 ,  H01L23/522 ,  G01K7/16 ,  H01L27/00 ,  H01L23/482 ,  H01L27/06

Abstract: One device disclosed herein includes, among other things, a substrate, a first resistor comprising a first phase transition material formed above the substrate, the first phase transition material exhibiting a first dielectric phase for temperatures less than a first phase transition temperature and a first semiconductor phase for temperatures greater than the first phase transition temperature, and logic to detect a transition of the first resistor to the first semiconductor phase.

公开(公告)号：US11316045B2

公开(公告)日：2022-04-26

申请号：US16691691

申请日：2019-11-22

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Anthony K. Stamper ,  Aaron L. Vallett ,  Steven M. Shank ,  John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (FETS) and methods of manufacture. The structure includes: a substrate material; at least one vertically oriented gate structure extending into the substrate material and composed of a gate dielectric material and conductive gate material; and vertically oriented source/drain regions extending into the substrate material and composed of conductive dopant material and a silicide on the source/drain regions.

公开(公告)号：US11264457B1

公开(公告)日：2022-03-01

申请号：US16953897

申请日：2020-11-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mark Levy ,  Siva P. Adusumilli ,  Steven M. Shank ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L21/763 ,  H01L27/06 ,  H01L21/762

Abstract: Semiconductor structures with electrical isolation and methods of forming a semiconductor structure with electrical isolation. A shallow trench isolation region, which contains a dielectric material, is positioned in a semiconductor substrate. A trench extendes through the shallow trench isolation region and to a trench bottom in the semiconductor substrate beneath the shallow trench isolation region. A dielectric layer at least partially fills the trench. A polycrystalline region, which is arranged in the semiconductor substrate, includes a portion that is positioned beneath the trench bottom.

公开(公告)号：US20210336005A1

公开(公告)日：2021-10-28

申请号：US16855236

申请日：2020-04-22

Applicant: GLOBALFOUNDRIES U.S. Inc

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L29/08 ,  H01L29/78

Abstract: The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.

公开(公告)号：US11158722B2

公开(公告)日：2021-10-26

申请号：US16730371

申请日：2019-12-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Vibhor Jain ,  Steven M. Shank ,  John J. Pekarik ,  Anthony K. Stamper

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/15 ,  H01L29/16 ,  H01L29/267 ,  H01L29/10

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with an oxygen lattice structure and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the substrate; at least one oxygen film separating the sub-collector region and the collector region; an emitter region adjacent to the collector region; and a base region adjacent to the emitter region.

公开(公告)号：US20210296122A1

公开(公告)日：2021-09-23

申请号：US16821228

申请日：2020-03-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Cameron Luce ,  Ramsey Hazbun ,  Mark Levy ,  Anthony K. Stamper ,  Alvin J. Joseph

IPC: H01L21/02 ,  H01L21/324 ,  H01L21/762

Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.

公开(公告)号：US20210151621A1

公开(公告)日：2021-05-20

申请号：US16686973

申请日：2019-11-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L31/074 ,  H01L31/028 ,  H01L31/18

Abstract: Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.

公开(公告)号：US11004878B2

公开(公告)日：2021-05-11

申请号：US16544074

申请日：2019-08-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  John J. Pekarik

IPC: H01L27/144 ,  H01L29/04 ,  H01L29/165 ,  H01L29/737 ,  H01L29/06 ,  H01L29/66 ,  H01L31/02 ,  H01L31/105 ,  H01L31/18 ,  H01L31/0312 ,  G01S7/481 ,  H03F3/08

Abstract: Structures including a photodiode and methods of fabricating such structures. A substrate has a top surface, a well, and a trench extending from the top surface to the well. A photodiode is positioned in the trench. The photodiode includes an electrode that is provided by a first portion of the well. A bipolar junction transistor has an emitter that is positioned over the top surface of the substrate and a subcollector that is positioned below the top surface of the substrate. The subcollector is provided by a second portion of the well.

公开(公告)号：US10931274B2

公开(公告)日：2021-02-23

申请号：US16252007

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain

IPC: H03K17/14 ,  G05D23/19 ,  G05D23/24 ,  G01K3/00 ,  H01C7/04

Abstract: One illustrative device includes, among other things, an active device comprising a first terminal, a first bias resistor connected to the first terminal, and a first resistor comprising a first phase transition material connected in parallel with the first bias transistor, wherein the first phase transition material exhibits a first low conductivity phase for temperatures less than a first phase transition temperature and a first high conductivity phase for temperatures greater than the first phase transition temperature.

公开(公告)号：US12170313B2

公开(公告)日：2024-12-17

申请号：US18324637

申请日：2023-05-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Steven M. Shank ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L21/763 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/737

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors (HBTs) with a buried trap rich region and methods of manufacture. The structure includes: a trap rich isolation region embedded within the bulk substrate; and a heterojunction bipolar transistor above the trap rich isolation region, with its sub-collector region separated by the trap rich isolation region by a layer of the bulk substrate.