-
公开(公告)号：US08728859B2
公开(公告)日：2014-05-20
申请号：US12855079
申请日：2010-08-12
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/143 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683 , H01L45/1691
摘要： An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal 1) of a semiconductor wafer, and includes a bottom and a sidewall. A sublithographic aperture is formed through the bottom of the non-sublithographic via and extends to a buried conductive material. The sublithographic aperture is filled with a conductive non-phase change material. Furthermore, phase change material is deposited within the non-sublithographic via.
摘要翻译： 所公开的示例性实施例是用于制造相变存储单元的方法。 该方法包括在绝缘衬底内形成非亚光刻通孔。 绝缘基板被嵌入与半导体晶片的第一金属化层（金属1）相同的层上，并且包括底部和侧壁。 通过非亚光刻通孔的底部形成亚光刻孔，并延伸到掩埋的导电材料。 亚光刻孔填充有导电非相变材料。 此外，相变材料沉积在非亚光刻通孔内。
-
公开(公告)号：US08686391B2
公开(公告)日：2014-04-01
申请号：US13612552
申请日：2012-09-12
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
摘要翻译： 提供一种制造电极的方法，其包括在电介质层的导电结构的顶部设置第一相变材料的柱; 或倒置结构; 在电介质层的上方形成绝缘材料，并邻近所述柱，其中所述第一绝缘材料的上表面与所述柱的上表面共面; 将所述柱的上表面凹陷在所述绝缘材料的上表面下方以提供凹腔; 以及在所述凹腔和所述绝缘材料的上表面之上形成第二相变材料，其中所述第二相变材料具有比所述第一相变材料更大的相电阻率。
-
33.发明申请HIGH ASPECT RATIO AND REDUCED UNDERCUT TRENCH ETCH PROCESS FOR A SEMICONDUCTOR SUBSTRATE 有权用于半导体衬底的高纵横比和降低的底切热蚀刻工艺公开(公告)号：US20130105947A1
公开(公告)日：2013-05-02
申请号：US13281715
申请日：2011-10-26
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L29/0657 , H01L21/30655 , H01L21/76898
摘要： A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.
摘要翻译： 在各向异性蚀刻工艺中使用氢氟烃气体作为聚合物沉积气体，其使用蚀刻剂气体和聚合物沉积气体的交替来蚀刻半导体衬底中的深沟槽。 氢氟烃气体可以在半导体衬底的顶表面上与聚合物的厚度一致的厚度在沟槽的侧壁上产生厚的富碳和含氢聚合物。 厚的富碳和含氢聚合物保护沟槽的侧壁，从而使硬掩模下方的底切最小化，而不降低整体速率。 在一些实施例中，可以实现整体蚀刻速率的改进。
-
公开(公告)号：US20130005053A1
公开(公告)日：2013-01-03
申请号：US13613313
申请日：2012-09-13
IPC分类号： H01L43/12
CPC分类号： G11C19/0808 , G11C11/14 , G11C11/161 , G11C11/1675
摘要： A method for forming a memory device includes forming a cavity having an inner surface with an undulating profile in a substrate, depositing a ferromagnetic material in the cavity, forming a reading element on the substrate proximate to a portion of the ferromagnetic material, and forming a writing element on the substrate proximate to a second portion of the ferromagnetic material.
摘要翻译： 一种用于形成存储器件的方法包括：形成具有在衬底中具有波状轮廓的内表面的空腔，在所述空腔中沉积铁磁材料，在所述衬底上形成接近所述铁磁材料的一部分的读取元件，以及形成 在基板上的写入元件靠近铁磁材料的第二部分。
-
公开(公告)号：US08288236B2
公开(公告)日：2012-10-16
申请号：US13345252
申请日：2012-01-06
IPC分类号： H01L21/336
CPC分类号： H01L51/001 , B82Y10/00 , H01L51/0048 , H01L51/0541 , H01L51/0558
摘要： A field effect transistor (FET) includes a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.
摘要翻译： 场效应晶体管（FET）包括由第一材料形成的漏极，由第一材料形成的源极，由将源极耦合到漏极的纳米结构形成的沟道以及在源极和漏极之间形成的栅极， 纳米结构。
-
公开(公告)号：US20120129313A1
公开(公告)日：2012-05-24
申请号：US13363549
申请日：2012-02-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric A. Joseph , Chung H. Lam , Bipin Rajendran , Alejandro G. Schrott , Yu Zhu
IPC分类号： H01L21/62
CPC分类号： H01L45/06 , H01L45/1233 , H01L45/1293 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.
摘要翻译： 一种存储单元结构及其形成方法。 该方法包括在电介质层内形成孔。 孔形成在导电底部电极的中心上方。 该方法包括沿孔的至少一个侧壁沉积绝热层。 绝热层将热量从相变电流隔离成孔的体积。 在一个实施例中，相变材料沉积在孔隙和隔热层的体积内。 在另一个实施方案中，孔隙电极形成在绝热层的孔隙和体积内，相变材料沉积在孔电极上方。 该方法还包括在相变材料上形成导电顶电极。
-
37.发明申请公开(公告)号：US20120038056A1
公开(公告)日：2012-02-16
申请号：US12853537
申请日：2010-08-10
申请人： Cyril Cabral, JR. , Sebastian U. Engelmann , Benjamin Fletcher , Eric A. Joseph , Satyanarayana V. Nitta
发明人： Cyril Cabral, JR. , Sebastian U. Engelmann , Benjamin Fletcher , Eric A. Joseph , Satyanarayana V. Nitta
IPC分类号： H01L23/528 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/31116 , H01L21/32136 , H01L21/32139 , H01L21/76804 , H01L21/76877 , H01L21/76885 , H01L23/5283 , H01L23/53214 , H01L23/53228 , H01L23/53242 , H01L23/53257 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.
摘要翻译： 本公开提供了形成到电气设备的互连的方法。 在一个实施例中，形成互连的方法包括在衬底上提供器件层，其中所述器件层包括至少一个电器件，在所述至少一个电器件上的入口电介质，以及与所述至少一个电器件电连接的触点 所述至少一个电气设备。 在器件层上形成互连金属层，并且在互连金属层的一部分上形成含钽蚀刻掩模。 蚀刻互连金属层以提供与至少一个电气设备连通的梯形互连。 梯形互连具有与器件层接触的第一表面，其具有比与含钽蚀刻掩模接触的梯形互连的第二表面更大的宽度。
-
公开(公告)号：US20110186800A1
公开(公告)日：2011-08-04
申请号：US13084088
申请日：2011-04-11
IPC分类号： H01L45/00
CPC分类号： H01L45/1625 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/1616 , H01L45/165 , H01L45/1666
摘要： A method of manufacturing an electrode is provided that includes providing a pillar of a first phase change material atop a conductive structure of a dielectric layer; or the inverted structure; forming an insulating material atop dielectric layer and adjacent the pillar, wherein an upper surface of the first insulating material is coplanar with an upper surface of the pillar; recessing the upper surface of the pillar below the upper surface of the insulating material to provide a recessed cavity; and forming a second phase change material atop the recessed cavity and the upper surface of the insulating material, wherein the second phase change material has a greater phase resistivity than the first phase change material.
摘要翻译： 提供一种制造电极的方法，其包括在电介质层的导电结构的顶部设置第一相变材料的柱; 或倒置结构; 在电介质层的上方形成绝缘材料，并邻近所述柱，其中所述第一绝缘材料的上表面与所述柱的上表面共面; 将所述柱的上表面凹陷在所述绝缘材料的上表面下方以提供凹腔; 以及在所述凹腔和所述绝缘材料的上表面之上形成第二相变材料，其中所述第二相变材料具有比所述第一相变材料更大的相电阻率。
-
公开(公告)号：US07972966B2
公开(公告)日：2011-07-05
申请号：US12468297
申请日：2009-05-19
IPC分类号： H01L21/311
CPC分类号： H01L21/32136 , H01L21/76834 , H01L21/76883 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1683
摘要： The present invention in one embodiment provides an etch method that includes providing a structure including a tungsten (W) portion and a titanium nitride (TiN) portion; applying a first etch feed gas of sulfur hexafluoride (SF6) and oxygen (O2), in which the ratio of sulfur hexafluoride (SF6) to oxygen (O2) ranges from 1:3.5 to 1:4.5; and applying a second etch feed gas of nitrogen trifluoride (NF3), helium (He) and chlorine (Cl2), in which the ratio of nitrogen trifluoride (NF3) to chlorine (Cl2) ranges from 1:5 to 2:5 and the ratio of helium (He) to nitrogen trifluoride (NF3) and chlorine (Cl2) ranges from 1:3 to 1:1.
摘要翻译： 本发明在一个实施例中提供了一种蚀刻方法，其包括提供包括钨（W）部分和氮化钛（TiN）部分的结构; 施加六氟化硫（SF 6）和氧（O 2）的第一蚀刻进料气体，其中六氟化硫（SF 6）与氧气（O 2）的比率为1:3.5至1:4.5; 并施加三氟化氮（NF3）与氯（Cl2）的比率为1:5〜2:5的三氟化氮（NF3），氦（He）和氯（Cl2）的第二蚀刻进料气体， 氦（He）与三氟化氮（NF 3）和氯（Cl 2）的比例为1:3-1:1。
-
公开(公告)号：US07906368B2
公开(公告)日：2011-03-15
申请号：US11771501
申请日：2007-06-29
IPC分类号： H01L21/06
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.
摘要翻译： 本发明的实施例包括形成非易失性相变存储器（PCM）单元的方法。 该方法包括形成至少一个底部电极; 在所述底部电极的上表面的至少一部分上形成至少一个相变材料层; 在所述相变材料层的上表面的至少一部分上形成至少一个加热层; 并且将加热器层成形为锥形，使得加热器层的上表面的横截面宽度大于与相变材料层接触的加热器层的底表面的横截面宽度。
-
-
-
-
-
-
-
-
-
搜索结果
76 条记录 (耗时 0.047 秒)
