公开(公告)号：US07135926B2

公开(公告)日：2006-11-14

申请号：US11239927

申请日：2005-09-29

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03F3/45

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US07034606B2

公开(公告)日：2006-04-25

申请号：US10841766

申请日：2004-05-07

Applicant: Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

Inventor： Mario Caresosa ,  Afshin Momtaz ,  Guangming Yin

IPC: G06G7/12

CPC classification number: H03G1/007 ,  H03F3/45188 ,  H03F3/45197 ,  H03F2203/45504 ,  H03F2203/45638 ,  H03G1/0029 ,  H03G1/0088

Abstract: An input processing circuit includes a first and second input transistors for receiving a differential pair of first and second input signals, respectively. At least one resistor is coupled between first terminals of the first and second input transistors. The input processing circuit includes a variable gain amplifier (VGA) circuit. At least one first transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. At least one second transistor has a gate terminal, and is coupled between the first terminals of the first and second input transistors. A gate switch is coupled to the gate terminal of the at least one second transistor. The at least one first transistor and the at least one second transistor adjust a gain of the input processing circuit in response to a control voltage. The control voltage is applied to the gate terminal of the at least one first transistor, and the control voltage is applied to the gate terminal of the at least one second transistor through the gate switch.

Abstract translation: 输入处理电路包括分别用于接收第一和第二输入信号的差分对的第一和第二输入晶体管。 至少一个电阻耦合在第一和第二输入晶体管的第一端之间。 输入处理电路包括可变增益放大器（VGA）电路。 至少一个第一晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 至少一个第二晶体管具有栅极端子，并且耦合在第一和第二输入晶体管的第一端子之间。 栅极开关耦合到至少一个第二晶体管的栅极端子。 所述至少一个第一晶体管和所述至少一个第二晶体管响应于控制电压调整所述输入处理电路的增益。 控制电压被施加到至少一个第一晶体管的栅极端子，并且通过栅极开关将控制电压施加到至少一个第二晶体管的栅极端子。

公开(公告)号：US06982583B2

公开(公告)日：2006-01-03

申请号：US10876790

申请日：2004-06-25

Applicant: Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

Inventor： Guangming Yin ,  Ichiro Fujimori ,  Armond Hairapetian

IPC: H03K3/356

CPC classification number: H03K3/3562 ,  H03K3/356043 ,  H03K17/693 ,  H03K19/09432 ,  H03K19/215

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems. The C3MOS structure enables the use of a power supply voltage that may be larger than the voltage required by the CMOS fabrication process, further enhancing the performance of the circuit.

Abstract translation: 用于实现超高速电路的各种电路技术使用以常规CMOS工艺技术制造的电流控制CMOS（C 3/4 MOS）逻辑。 包括逆变器/缓冲器，电平移位器，NAND，NOR，异或门，锁存器，触发器等的整个逻辑元件族都使用C 3 MOS技术实现。 通过将高速C“3”MOS逻辑与低功耗常规CMOS逻辑相结合，实现了每个电路应用的功耗和速度之间的最佳平衡。 组合的三极管/ CMOS逻辑允许诸如光纤通信系统中使用的高速收发器之类的电路的更大集成。 C 3 O 3 MOS结构能够使用可能大于CMOS制造工艺所需的电压的电源电压，进一步提高电路的性能。

公开(公告)号：US06980053B2

公开(公告)日：2005-12-27

申请号：US10852275

申请日：2004-05-24

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/30

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US20050258900A1

公开(公告)日：2005-11-24

申请号：US10852275

申请日：2004-05-24

Applicant: Mario Caresosa ,  Guangming Yin

Inventor： Mario Caresosa ,  Guangming Yin

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/30

CPC classification number: H03F3/4569 ,  H03F3/45197 ,  H03F3/45744 ,  H03F2200/78 ,  H03F2203/45074 ,  H03F2203/45086 ,  H03F2203/45482 ,  H03F2203/45486 ,  H03G1/0088 ,  H03G3/3036 ,  H03G3/3052

Abstract: A method and apparatus for adaptively controlling a variable gain amplifier (VGA). The operation of the VGA is separated into a low gain mode and a high gain mode and the mode in which the VGA is currently operating in is adaptively sensed. A threshold voltage is compared to a control voltage of the VGA; if the VGA is currently operating in the low gain mode and the control voltage is higher than the threshold voltage, the VGA is switched from the low gain mode to the high gain mode; and if the VGA is currently operating in the high gain mode and the control voltage is lower than the threshold voltage, the VGA is switched from the high gain mode to the low gain mode.

Abstract translation: 一种用于自适应地控制可变增益放大器（VGA）的方法和装置。 VGA的操作被分为低增益模式和高增益模式，并且自适应地感测VGA当前正在操作的模式。 将门限电压与VGA的控制电压进行比较; 如果VGA当前处于低增益模式并且控制电压高于阈值电压，则VGA从低增益模式切换到高增益模式; 如果VGA当前处于高增益模式并且控制电压低于阈值电压，则VGA从高增益模式切换到低增益模式。

公开(公告)号：US20050190004A1

公开(公告)日：2005-09-01

申请号：US11120738

申请日：2005-05-03

Applicant: Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

Inventor： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC: H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H03B1/00

CPC classification number: H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract translation: 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US20050134310A1

公开(公告)日：2005-06-23

申请号：US11057968

申请日：2005-02-15

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03D13/00 ,  H03F3/45 ,  H03K19/21 ,  H04L7/033

CPC classification number: H03D13/003 ,  H03K19/215 ,  H04L7/033

Abstract: Aspects of the invention provide a fast one level zero-current-state XOR gate. An embodiment of the invention provides a first pair of differentially configured transistors and a level shifting resistor coupled to the first pair of differentially configured transistors. The one level zero-current-state XOR gate may also include a second pair of differentially configured transistors. A core of the XOR gate may be coupled to outputs of the first and the second pairs of differentially configured transistors.

公开(公告)号：US5614864A

公开(公告)日：1997-03-25

申请号：US536405

申请日：1995-09-29

Applicant: Frederic M. Stubbe ,  Daryush Shamlou ,  Kashif A. Ahmed ,  Guangming Yin

Inventor： Frederic M. Stubbe ,  Daryush Shamlou ,  Kashif A. Ahmed ,  Guangming Yin

IPC: H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45932 ,  H03F2203/45528

Abstract: A converter for converting a single-ended input V.sub.IN to a differential output signal V.sub.OUT through positive and negative output terminals is disclosed. The converter comprises a fully differential amplifier with one of its input terminals coupled to the single-ended input and its other input terminal coupled to a fixed voltage. The converter also has a first resistor ("R.sub.1 ") coupled between the single-ended input and the positive input terminal of the fully differential amplifier, a second resistor ("R.sub.2 ") coupled between the fixed voltage and the negative input terminal of the fully differential amplifier, a third resistor ("R.sub.3 ") coupled between the positive input terminal and the negative output terminal of the fully differential amplifier, and a fourth resistor ("R.sub.4 ") coupled between the negative input terminal and the positive output terminal, wherein the values of such resistors are governed by: ##EQU1## The same principles can be applied to differential-to-single-ended converters as well.

Abstract translation: 公开了一种通过正和负输出端将单端输入VIN转换为差分输出信号VOUT的转换器。 该转换器包括全差分放大器，其一个输入端耦合到单端输入端，其另一输入端耦合到一固定电压。 转换器还具有耦合在全差分放大器的单端输入端和正输入端之间的第一电阻（“R1”），耦合在固定电压和负输入端之间的第二电阻（“R2”） 全差分放大器，耦合在全差分放大器的正输入端和负输出端之间的第三电阻（“R3”）和耦合在负输入端和正输出端之间的第四电阻（“R4”）， 其中这些电阻的值由以下控制：相同的原理也可应用于差分到单端转换器。

公开(公告)号：US07577171B2

公开(公告)日：2009-08-18

申请号：US10361463

申请日：2003-02-10

Applicant: Mohammad Nejad ,  Guangming Yin ,  Ali Ghiasi

Inventor： Mohammad Nejad ,  Guangming Yin ,  Ali Ghiasi

IPC: H04J3/02

CPC classification number: H04L5/023 ,  H04L7/0008

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines. The transmit data clock is carried on a line that is centered with respect to the first group of lines and the second group of lines such that it resides between the first group of lines and the second group of lines. The interface may also interface a first receive data demultiplexing integrated circuit and a second receive data demultiplexing integrated circuit.

Abstract translation: 多比特流接口将第一发送数据多路复用集成电路和第二发送数据多路复用集成电路接口。 多比特流接口包括多个发送比特流的接口，每个发送比特流以接口比特率携带相应的比特流。 该接口还包括以对应于接口比特率的一半的频率工作的发送数据时钟。 第一发送数据复用集成电路以第一比特率从通信ASIC接收第一多个发送比特流。 第二发送数据复用集成电路以线路比特率产生单个比特流输出。 所述多个发送比特流的接口被分成第一组和第二组，其中所述第一组在第一组线路上承载，并且所述第二组在第二组线路上承载。 发送数据时钟在相对于第一组线路和第二组线路居中的线路上承载，使得它位于第一组线路组与第二组线路组之间。 接口还可以将第一接收数据解复用集成电路和第二接收数据解复用集成电路接口。

公开(公告)号：US07386084B2

公开(公告)日：2008-06-10

申请号：US10456803

申请日：2003-06-06

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC classification number: H03L7/091 ,  H03K5/135 ,  H04L7/033

Abstract: Aspects of the pattern-independent phase adjustment system includes a single output data XOR gate coupled to a differential input data signal and a bias voltage through a first variable resistor. A single output reference XOR gate may be coupled to a latched differential input signal and the bias voltage through a second variable resistor. At least one latch may be coupled to at least one differential input of the data and reference XOR gate. The single output of the data XOR gate may be a data output of a clock and data recovery circuit (CDR) and the single output of the reference XOR gate may be a reference output of the clock and CDR. No current may flow at the data output of the data XOR gate and the reference output of the reference XOR gate when there are no transitions occurring at an input of the phase detector.

Abstract translation: 独立于图形的相位调整系统的方面包括通过第一可变电阻器耦合到差分输入数据信号和偏置电压的单个输出数据XOR门。 单个输出参考XOR门可以通过第二可变电阻耦合到锁存的差分输入信号和偏置电压。 至少一个锁存器可以耦合到数据和参考XOR门的至少一个差分输入。 数据异或门的单个输出可以是时钟和数据恢复电路（CDR）的数据输出，并且参考异或门的单个输出可以是时钟和CDR的参考输出。 当在相位检测器的输入处没有发生转换时，数据XOR门的数据输出和参考XOR门的参考输出都不会流过电流。