公开(公告)号：US20190001695A1

公开(公告)日：2019-01-03

申请号：US16125701

申请日：2018-09-08

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Alexander Govyadinov ,  Adam L. Ghozeil ,  Boon Bing Ng ,  Patrick Leonard ,  Raymond Connolly

IPC: B41J2/175 ,  B41J2/045 ,  B41J2/14 ,  B41J2/18

CPC classification number: B41J2/17566 ,  B41J2/04541 ,  B41J2/0458 ,  B41J2/1404 ,  B41J2/14072 ,  B41J2/14153 ,  B41J2/175 ,  B41J2/18 ,  B41J2002/14467 ,  B41J2202/11 ,  B41J2202/12

Abstract: A print head has a fluid slot and a sensing chamber having a first port connected to the fluid slot and a second port. The sensing chamber contains an ink level sensor. A circulation passage extends from the fluid slot and is fluidly coupled to the second port. A fluid pump circulates fluid through the circulation passage.

公开(公告)号：US20180268905A1

公开(公告)日：2018-09-20

申请号：US15986531

申请日：2018-05-22

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  B41J2/175 ,  G11C19/28

CPC classification number: G11C16/06 ,  B41J2/17546 ,  G11C8/12 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US09773556B2

公开(公告)日：2017-09-26

申请号：US15114823

申请日：2014-01-31

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  Hang Ru Goy

IPC: G11C11/34 ,  G11C16/08 ,  G11C8/04 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C8/04 ,  G11C8/08 ,  G11C8/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11514 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/7841

Abstract: Three-dimensional addressing for erasable programmable read only memory (EPROM) can include a number of EPROM banks, a number of shift registers, a row select data signal, a column select data signal, and a bank select data signal.

公开(公告)号：US20170213596A1

公开(公告)日：2017-07-27

申请号：US15327927

申请日：2014-07-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Thida Ma Win ,  Ning Ge ,  Jose Jehrome Rando

IPC: G11C16/06 ,  B41J2/175 ,  G11C19/28

CPC classification number: G11C16/06 ,  B41J2/17546 ,  G11C8/12 ,  G11C16/08 ,  G11C19/00 ,  G11C19/28

Abstract: A split memory bank may comprise a number of memory matrices forming a memory bank and a shift register in which the shift register physically separates the matrices. An integrated circuit may comprise a number of shift registers and a plurality of memory matrices forming a memory bank in which the matrices are spatially separated by the shift register. An integrated printhead may comprise a number of memory banks each comprising a plurality of memory matrices and a number of shift registers in which each shift register spatially separates a number of the matrices.

公开(公告)号：US12103303B2

公开(公告)日：2024-10-01

申请号：US17835672

申请日：2022-06-08

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng

IPC: B41J2/045 ,  B41J2/175

CPC classification number: B41J2/04541 ,  B41J2/17546 ,  B41J2202/13 ,  B41J2202/17

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a fire line, a plurality of memory elements, a first switch, and a plurality of second switches. The first switch is electrically coupled between the fire line and a first side of each memory element of the plurality of memory elements. Each second switch is electrically coupled to a second side of a respective memory element of the plurality of memory elements.

公开(公告)号：US11969999B2

公开(公告)日：2024-04-30

申请号：US18099517

申请日：2023-01-20

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Boon Bing Ng ,  Mohan Kumar Sudhakar

IPC: B41J29/38 ,  B41J2/045

CPC classification number: B41J2/0455 ,  B41J2/04541 ,  B41J2/04586

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an ID line, a fire line, a discharge path, a memory element, and a latch. The memory element is electrically coupled to the fire line and the discharge path. The latch disables the discharge path in response to a first logic level on the ID line and enables the discharge path in response to a second logic level on the ID line.

公开(公告)号：US11969997B2

公开(公告)日：2024-04-30

申请号：US17847788

申请日：2022-06-23

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng

IPC: B41J29/38 ,  B41J2/045 ,  B41J2/175

CPC classification number: B41J2/04541 ,  B41J2/17546 ,  B41J2202/13 ,  B41J2202/17

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes a plurality of first data lines, a second data line, a first memory element, and a second memory element. The first memory element is enabled in response to first data on the plurality of first data lines. The second memory element is enabled in response to second data on the second data line.

公开(公告)号：US11590753B2

公开(公告)日：2023-02-28

申请号：US16959085

申请日：2019-04-19

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Mohan Kumar Sudhakar

IPC: B41J29/38 ,  B41J2/045

Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an ID line, a fire line, a discharge path, a memory element, and a latch. The memory element is electrically coupled to the fire line and the discharge path. The latch disables the discharge path in response to a first logic level on the ID line and enables the discharge path in response to a second logic level on the ID line.

公开(公告)号：US11590752B2

公开(公告)日：2023-02-28

申请号：US16768588

申请日：2019-07-31

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： James Michael Gardner ,  Boon Bing Ng

IPC: B41J2/045 ,  G06F3/12 ,  G06F13/16 ,  G11C7/10 ,  G11C16/10 ,  G11C16/26

Abstract: A memory circuit for a print component including plurality of I/O pads, including a first analog pad and a second analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component, including an analog signal path connected to the first analog pad and the second analog pad, the first analog pad electrically isolated from the second analog pad to interrupt the analog signal path to the print component. The memory circuit further includes a memory component to store memory values associated with the print component, and a control circuit to, in response to a sequence of operating signals received by the I/O pads representing a memory read, provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

公开(公告)号：US11511539B2

公开(公告)日：2022-11-29

申请号：US16771080

申请日：2019-02-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Erik D. Ness ,  James Michael Gardner

IPC: B41J2/045

Abstract: In some examples, a fluid dispensing device component includes a plurality of fluidic dies each comprising a memory, a plurality of control inputs to provide respective control information to respective fluidic dies of the plurality of fluidic dies, and a data bus connected to the plurality of fluidic dies, the data bus to provide data of the memories of the plurality of fluidic dies to an output of the fluid dispensing device component.