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公开(公告)号：US20160254448A1
公开(公告)日：2016-09-01
申请号：US15032913
申请日：2013-11-12
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Byungjoon Choi , Jianhua Yang , R. Stanley Williams , Gary Gibson , Warren Jackson
IPC: H01L45/00
CPC classification number: H01L45/1226 , H01L27/2418 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/14 , H01L45/145 , H01L45/146 , H01L45/16
Abstract: A nonlinear memristor device with a three-layer selector includes a memristor in electrical series with a three-layer selector. The memristor comprises at least one electrically conducting layer and at least one electrically insulating layer. The three-layer selector comprises a three-layer structure selected from the group consisting of XN—XO—XN; XN—YO—ZN: XN—YO—XN; XO—XN—XO; XO—YN—XO; XO—YN—ZO; XO—YO—XO; XO—YO—ZO; XN—YN—ZN; and XN—YN—XN, X represents a compound-forming metal different from Y and Z.
Abstract translation: 具有三层选择器的非线性忆阻器装置包括与三层选择器电连接的忆阻器。 忆阻器包括至少一个导电层和至少一个电绝缘层。 三层选择器包括从XN-XO-XN组成的组中选择的三层结构; XN-YO-ZN：XN-YO-XN; XO-XN-XO; XO-YN-XO; XO-YN-ZO; XO-YO-XO; XO-YO-ZO; XN-YN-ZN; 和XN-YN-XN，X表示不同于Y和Z的化合物形成金属。
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公开(公告)号：US20160225823A1
公开(公告)日：2016-08-04
申请号：US14916766
申请日：2013-09-16
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Shih-Yuan Wang , Jianhua Yang , R. Stanley Williams
CPC classification number: H01L27/2463 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/1616 , H01L45/1683
Abstract: A switching resistance memory device with an interfacial channel includes a stack made of a layer of a first material and a layer of a second material. The layers form an interface, with the interface comprising the interfacial channel along which charged species can travel. A first electrode contacts a first edge of the stack, and a second electrode contacts a second edge of the stack.
Abstract translation: 具有界面通道的开关电阻存储器件包括由第一材料层和第二材料层构成的叠层。 这些层形成界面，其界面包括带电物种可以沿其移动的界面通道。 第一电极接触堆叠的第一边缘，并且第二电极接触堆叠的第二边缘。
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公开(公告)号：US20160218285A1
公开(公告)日：2016-07-28
申请号：US14914808
申请日：2013-09-05
Applicant: HEWLETT-PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Shih-Yuan Wang , Jianhua Yang , Minxian Max Zhang , Alexandre M. Bratkovski , R. Stanley Williams
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/08 , H01L45/12 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1608
Abstract: A memristor structure may be provided that includes a first electrode, a second electrode, and a buffer layer disposed on the first electrode. The memristor structure may include a switching layer interposed between the second electrode and the buffer layer to form, when a voltage is applied, a filament or path that extends from the second electrode to the buffer layer and to form a Schottky-like contact or a heterojunction between the filament and the buffer layer.
Abstract translation: 可以提供一种忆阻器结构，其包括设置在第一电极上的第一电极，第二电极和缓冲层。 忆阻器结构可以包括插入在第二电极和缓冲层之间的开关层，当施加电压时，形成从第二电极延伸到缓冲层并形成肖特基状接触的长丝或路径 灯丝与缓冲层之间的异质结。
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公开(公告)号：US20190214085A1
公开(公告)日：2019-07-11
申请号：US16353451
申请日：2019-03-14
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jianhua Yang , Miao Hu , John Paul Strachan , Ning Ge
CPC classification number: G11C13/0069 , G06F3/03 , G06G7/16 , G11C13/0021 , G11C13/003 , G11C13/0064 , G11C2213/79
Abstract: A memristive dot-product system for vector processing is described. The memristive dot-product system includes a crossbar array having a number of memory elements. Each memory element includes a memristor. Each memory element includes a transistor. The system also includes a vector input register. The system also includes a vector output register.
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公开(公告)号：US10319441B2
公开(公告)日：2019-06-11
申请号：US16220647
申请日：2018-12-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ning Ge , Jianhua Yang , John Paul Strachan , Miao Hu
Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.
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Patent Agency Ranking
公开(公告)号：US20190139605A1
公开(公告)日：2019-05-09
申请号：US16220647
申请日：2018-12-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ning Ge , Jianhua Yang , John Paul Strachan , Miao Hu
Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second sat of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.
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公开(公告)号：US10249356B2
公开(公告)日：2019-04-02
申请号：US15522344
申请日：2014-10-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ning Ge , John Paul Strachan , Jianhua Yang , Miao Hu
Abstract: A method of obtaining a dot product includes applying a programming signal to a number of capacitive memory devices coupled at a number of junctions formed between a number of row lines and a number of column lines. The programming signal defines a number of values within a matrix. The method further includes applying a vector signal. The vector signal defines a number of vector values to be applied to the capacitive memory devices.
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公开(公告)号：US10074695B2
公开(公告)日：2018-09-11
申请号：US15500084
申请日：2014-12-19
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Jianhua Yang , Stanley Williams , Max Zhang , Zhiyong Li
CPC classification number: H01L27/26 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L47/005
Abstract: A negative differential resistance (NDR) device for non-volatile memory cells in crossbar arrays is provided. Each non-volatile memory cell is situated at a crosspoint of the array. Each non-volatile memory cell comprises a switching layer in series with an NDR material containing fast diffusive atoms that are electrochemically inactive. The switching layer is positioned between two elec-trodes.
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公开(公告)号：US10026477B2
公开(公告)日：2018-07-17
申请号：US15329845
申请日：2015-01-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Jianhua Yang , Ning Ge , John Paul Strachan , Gary Gibson , Warren Jackson
Abstract: In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first voltage level is removed to activate a relaxation time for the volatile selector. The relaxation time is defined as the time the first volatile selector transitions from the high conduction state back to the low conduction state. The volatile selector is switched with a second voltage level of opposite polarity to the first voltage level to significantly reduce the relaxation time of the volatile selector.
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公开(公告)号：US10008264B2
公开(公告)日：2018-06-26
申请号：US15521542
申请日：2014-10-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Ning Ge , Jianhua Yang , John Paul Strachan , Miao Hu
CPC classification number: G11C13/0069 , G06F17/11 , G06F17/16 , G06G7/16 , G11C7/1006 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C2213/15 , G11C2213/77
Abstract: A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.
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