公开(公告)号：US10346701B2

公开(公告)日：2019-07-09

申请号：US15695681

申请日：2017-09-05

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  NANYANG TECHNOLOGICAL UNIVERSITY

Inventor： Hao Yu ,  Yuhao Wang ,  Leibin Ni ,  Wei Yang ,  Junfeng Zhao ,  Shihai Xiao

IPC: G06K9/00 ,  G06K9/62

Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.

公开(公告)号：US10223273B2

公开(公告)日：2019-03-05

申请号：US15638582

申请日：2017-06-30

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  Fudan University

Inventor： RenHua Yang ,  Junfeng Zhao ,  Wei Yang ,  Yuangang Wang ,  Yinyin Lin

IPC: G06F12/02 ,  G06F12/0868 ,  G06F13/28 ,  G06F11/14 ,  G06F12/0802 ,  G06F12/109 ,  G11C11/406

Abstract: A memory access method, a storage-class memory, and a computer system are provided. The computer system includes a memory controller and a hybrid memory, and the hybrid memory includes a dynamic random access memory (DRAM) and a storage-class memory (SCM). The memory controller sends a first access instruction to the DRAM and the SCM. When determining that a first memory cell set that is of the DRAM and to which a first address in the received first access instruction points includes a memory cell whose retention time is shorter than a refresh cycle of the DRAM, the SCM may obtain a second address having a mapping relationship with the first address. Further, the SCM converts, according to the second address, the first access instruction into a second access instruction for accessing the SCM, to implement access to the SCM.

公开(公告)号：US10083749B2

公开(公告)日：2018-09-25

申请号：US15412795

申请日：2017-01-23

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhen Li ,  Qiang He ,  Xiangshui Miao ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

IPC: G11C11/56 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C7/02 ,  G11C11/5678 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0092

Abstract: A data storage method applying to a phase change memory and the phase change memory are provided. After obtaining to-be-stored data, the phase change memory (PCM) generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal includes at least two contiguous pulses. Intervals between the at least two contiguous pulses are the same. The intervals between the at least two contiguous pulses have a value determined according to the to-be-stored data. The PCM applies the erase pulse signal to a storage unit of the PCM to enable the storage unit to change to a crystalline state. Further, the write pulse signal is applied to the storage unit to enable the storage unit to change to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.

公开(公告)号：US20180012095A1

公开(公告)日：2018-01-11

申请号：US15695681

申请日：2017-09-05

Applicant: HUAWEI TECHNOLOGIES CO.,LTD. ,  NANYANG TECHNOLOGICAL UNIVERSITY

Inventor： Hao Yu ,  Yuhao Wang ,  Leibin Ni ,  Wei Yang ,  Junfeng Zhao ,  Shihai Xiao

IPC: G06K9/00 ,  G06K9/62

CPC classification number: G06K9/00973 ,  G06K9/00 ,  G06K9/6201

Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.

公开(公告)号：US09824739B2

公开(公告)日：2017-11-21

申请号：US15406209

申请日：2017-01-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Kai Yang ,  Junfeng Zhao ,  Yuangang Wang ,  Wei Yang ,  Yinyin Lin ,  Yarong Fu

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607 ,  G11C19/0808 ,  G11C19/0841 ,  G11C19/0866

Abstract: A magnetic storage apparatus is disclosed, and is configured to access data. The magnetic storage apparatus includes a magnetic storage track, a first write apparatus, a second write apparatus, and a drive apparatus. The first write apparatus and the second write apparatus are located at different positions on the magnetic storage track. The first write apparatus is configured to write first data “0” or second data “1”. The second write apparatus is configured to write third data “2” and fourth data “3”.

公开(公告)号：US09800334B2

公开(公告)日：2017-10-24

申请号：US15070212

申请日：2016-03-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiaowen Dong ,  Junfeng Zhao ,  Wei Yang

IPC: H04B10/116 ,  G01S11/12

CPC classification number: H04B10/116 ,  G01S11/12

Abstract: A positioning method based on a visible light source, a mobile terminal, and a controller. The method includes acquiring, by a visible light source controller, geographical position attribute information of a position at which a visible light source array is located, determining, by the visible light source controller according to a preset correspondence between geographical position attribute information of a position at which a visible light source array is located and a visible light source array pattern, a visible light source array pattern corresponding to the acquired geographical position attribute information, and controlling, by the visible light source controller according to the determined visible light source array pattern, the luminance state of each visible light source included in the visible light source array. Hence the method reduces the complexity of a positioning process.

公开(公告)号：US09767900B2

公开(公告)日：2017-09-19

申请号：US15266367

申请日：2016-09-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xiangshui Miao ,  Yi Li ,  Yaxiong Zhou ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463

Abstract: A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple resistive random access memories, multiple field effect transistor switches and a voltage converter. The logical operation array is set for performing logical operation and enable to storage output level signal in one resistive random access memory after the logical operation

公开(公告)号：US20170263295A1

公开(公告)日：2017-09-14

申请号：US15607360

申请日：2017-05-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Wei Yang ,  Junfeng Zhao

IPC: G11C8/16 ,  G06F3/06

CPC classification number: G11C8/16 ,  G06F3/0659 ,  G11C8/10

Abstract: A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.

公开(公告)号：US09653178B2

公开(公告)日：2017-05-16

申请号：US15133452

申请日：2016-04-20

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yinyin Lin ,  Zhulin Wei ,  Junfeng Zhao ,  Wei Yang ,  Yarong Fu ,  Kai Yang

IPC: G11C11/15 ,  G11C19/08

CPC classification number: G11C19/0841 ,  G11C11/15 ,  G11C11/161 ,  G11C11/1675 ,  G11C19/0808

Abstract: A storage device, a memory, and a method for controlling a storage device, where the storage device includes a comb-shaped magnetic track, a first drive circuit, a second drive circuit, a first drive port, and a second drive port, where the comb-shaped magnetic track includes a first storage area, a second storage area, and a comb handle, and the first storage area and the second storage area include more than two memory bars.

公开(公告)号：US20170133090A1

公开(公告)日：2017-05-11

申请号：US15412795

申请日：2017-01-23

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhen Li ,  Qiang He ,  Xiangshui Miao ,  Ronggang Xu ,  Junfeng Zhao ,  Zhulin Wei

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C7/02 ,  G11C11/5678 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0092

Abstract: A data storage method applying to a phase change memory and the phase change memory are provided. After obtaining to-be-stored data, the phase change memory (PCM) generates an erase pulse signal and a write pulse signal according to the to-be-stored data. The to-be-stored data is multi-bit data. The write pulse signal includes at least two contiguous pulses. Intervals between the at least two contiguous pulses are the same. The intervals between the at least two contiguous pulses have a value determined according to the to-be-stored data. The PCM applies the erase pulse signal to a storage unit of the PCM to enable the storage unit to change to a crystalline state. Further, the write pulse signal is applied to the storage unit to enable the storage unit to change to an amorphous state corresponding to a first resistance value, where the amorphous state represents the to-be-stored data.