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公开(公告)号：US20160173328A1
公开(公告)日：2016-06-16
申请号：US15014184
申请日：2016-02-03
Applicant: Huawei Technologies Co., Ltd.
Inventor： Wentao Bao , Binzhang Fu , Mingyu Chen , Lixin Zhang
CPC classification number: H04L41/0803 , H04L12/42 , H04L12/44 , H04L12/462 , H04L41/142 , H04L41/145 , H04L43/045 , H04L45/02
Abstract: A server connection method and system, which relates to the field of communications technologies, such that servers of a same specification are used to implement an optimal network, thereby reducing complexity of routing implementation which includes, providing ten servers, where each server includes five nodes, and the five nodes of each server are connected head-to-tail in series in a same connection manner, and connecting five nodes of any server in five of the ten servers to five nodes of each of the remaining five servers in a one-to-one correspondence manner, in order to form an optimal network of a Hoffman-Singleton graph.
Abstract translation: 一种与通信技术领域相关的服务器连接方法和系统，使得相同规范的服务器被用于实现最佳网络，从而降低路由实现的复杂性，其中包括提供十个服务器，其中每个服务器包括五个节点 并且每个服务器的五个节点以相同的连接方式串联连接，并将十个服务器中的五个服务器中的五个服务器中的五个节点连接到其余五个服务器中的每个服务器的五个节点， 以形成Hoffman-Singleton图的最佳网络。
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公开(公告)号：US20150212944A1
公开(公告)日：2015-07-30
申请号：US14680262
申请日：2015-04-07
Applicant: Huawei Technologies Co. Ltd.
Inventor： Mingyang Chen , Mingyu Chen , Zehan Cui , Licheng Chen
IPC: G06F12/08
CPC classification number: G06F12/0862 , G06F12/0866 , G06F17/30132 , G06F2212/1024 , G06F2212/312 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
Abstract: A method and an apparatus for pushing memory data from a memory to a push destination storage used to store data prefetched by a central processing unit (CPU) in a computing system are disclosed. In the method, a memory controller of the computing system periodically generates a push command according to a push period. Then the memory controller acquires a push parameter of to-be-pushed data according to the push command and sends at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory. After receiving the to-be-pushed data that is sent according to the at least one memory access request by the memory, the memory controller buffers the to-be-pushed data and pushes the to-be-pushed data from the data buffer to the push destination storage.
Abstract translation: 公开了一种用于将存储器数据从存储器推送到用于存储由计算系统中的中央处理单元（CPU）预取的数据的推送目的地存储器的方法和装置。 在该方法中，计算系统的存储器控制器根据推送周期周期性地产生推送命令。 然后，存储器控制器根据推送命令获取待推送数据的推送参数，并根据推送参数向存储器发送至少一个存储器访问请求，其中至少一个存储器访问请求被用于请求 从存储器中推送数据。 存储器控制器在接收到根据存储器的至少一个存储器访问请求发送的被推送数据之后，缓冲被推送的数据并将待推送的数据从数据缓冲器推送到 推送目的地存储。
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公开(公告)号：US11010056B2
公开(公告)日：2021-05-18
申请号：US16415940
申请日：2019-05-17
Applicant: Huawei Technologies Co., Ltd.
Inventor： Fei Xia , Mingyu Chen , Dejun Jiang , Jin Xiong
IPC: G06F3/06 , G06F12/0871 , G06F12/121 , G06F12/0868 , G06F12/00
Abstract: A data operating method, device, and system are provided and relate to the computer field, so as to resolve a prior-art problem of low efficiency of performing a data operation on a block device by a CPU. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.
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公开(公告)号：US20200150872A1
公开(公告)日：2020-05-14
申请号：US16744795
申请日：2020-01-16
Applicant: Huawei Technologies Co., Ltd.
Inventor： Zehan Cui , Mingyu Chen , Yao Liu , Yuan Ruan
Abstract: In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.
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公开(公告)号：US20190272099A1
公开(公告)日：2019-09-05
申请号：US16415940
申请日：2019-05-17
Applicant: Huawei Technologies Co., Ltd.
Inventor： Fei Xia , Mingyu Chen , Dejun Jiang , Jin Xiong
IPC: G06F3/06 , G06F12/0871 , G06F12/0868 , G06F12/121
Abstract: A data operating method, device, and system are provided and relate to the computer field, so as to resolve a prior-art problem of low efficiency of performing a data operation on a block device by a CPU. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.
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Patent Agency Ranking
公开(公告)号：US10320606B2
公开(公告)日：2019-06-11
申请号：US15014184
申请日：2016-02-03
Applicant: Huawei Technologies Co., Ltd.
Inventor： Wentao Bao , Binzhang Fu , Mingyu Chen , Lixin Zhang
Abstract: A server connection method and system, which relates to the field of communications technologies, such that servers of a same specification are used to implement an optimal network, thereby reducing complexity of routing implementation which includes, providing ten servers, where each server includes five nodes, and the five nodes of each server are connected head-to-tail in series in a same connection manner, and connecting five nodes of any server in five of the ten servers to five nodes of each of the remaining five servers in a one-to-one correspondence manner, in order to form an optimal network of a Hoffman-Singleton graph.
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公开(公告)号：US20170148422A1
公开(公告)日：2017-05-25
申请号：US15426356
申请日：2017-02-07
Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
Inventor： Yongbing Huang , Mingyu Chen , Zehan Cui , Shihai Xiao
CPC classification number: G09G5/395 , G09G3/3611 , G09G3/3688 , G09G5/399 , G09G2310/04 , G09G2320/103 , G09G2330/021 , G09G2340/0435 , G09G2360/18
Abstract: A refresh control method and apparatus of a display device are disclosed, where the method includes: (201) periodically generating, a first refresh signal, and outputting an image frame for display that is stored in a frame buffer to a display panel; and (202) generating, a second refresh signal when determining that the image frame for display that is stored in the frame buffer changes, and outputting the image frame for display that is stored in the frame buffer to the display panel. A generation frequency of the second refresh signal is far less than a frequency required to ensure timely display of an image frame. In addition, an operation of refreshing an image frame is triggered by using an event, which may ensure timely display of the image frame, and avoid an unnecessary refresh operation, so as to reduce system resource consumption and memory consumption.
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公开(公告)号：US09632938B2
公开(公告)日：2017-04-25
申请号：US14680262
申请日：2015-04-07
Applicant: Huawei Technologies Co., Ltd.
Inventor： Mingyang Chen , Mingyu Chen , Zehan Cui , Licheng Chen
IPC: G06F12/08 , G06F12/0862 , G06F17/30 , G06F12/0866
CPC classification number: G06F12/0862 , G06F12/0866 , G06F17/30132 , G06F2212/1024 , G06F2212/312 , G06F2212/602 , G06F2212/6022 , G06F2212/6028
Abstract: A method and an apparatus for pushing memory data from a memory to a push destination storage used to store data prefetched by a central processing unit (CPU) in a computing system are disclosed. In the method, a memory controller of the computing system periodically generates a push command according to a push period. Then the memory controller acquires a push parameter of to-be-pushed data according to the push command and sends at least one memory access request to memory according to the push parameter, where the at least one memory access request is used to request the to-be-pushed data from the memory. After receiving the to-be-pushed data that is sent according to the at least one memory access request by the memory, the memory controller buffers the to-be-pushed data and pushes the to-be-pushed data from the data buffer to the push destination storage.
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公开(公告)号：US20170075818A1
公开(公告)日：2017-03-16
申请号：US15343693
申请日：2016-11-04
Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
Inventor： Yao Liu , Yongbing Huang , Mingyu Chen , Zehan Cui , Licheng Chen , Yuan Ruan
IPC: G06F12/1027 , G06F12/1009 , G06F3/06
CPC classification number: G06F12/1027 , G06F3/0608 , G06F3/0619 , G06F3/0647 , G06F3/0652 , G06F3/0664 , G06F3/0685 , G06F12/1009 , G06F2212/1024 , G06F2212/684
Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.
Abstract translation: 一种存储器管理方法和装置，其中所述方法包括：接收存储器访问请求，其中所述存储器访问请求携带虚拟地址; 如果在翻译后备缓冲器TLB和存储器中找到与虚拟地址相对应的页表条目，则确定虚拟地址的页面错误类型; 如果虚拟地址的页面错误类型是由空白页引起的页面错误，其中由空白页引起的页面错误意味着没有对应的页面被分配给虚拟地址，则将对应的页面分配给虚拟地址; 以及将与虚拟地址相对应的页表条目更新到存储器和TLB。 当出现空白页引起的页面错误时，内存管理器不会生成页面错误，但会将相应的页面分配给虚拟地址。 因此，页面错误的发生量减少，从而提高存储器管理效率。
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40.发明申请Memory Access Processing Method, Memory Chip, and System Based on Memory Chip Interconnection 有权存储器存取处理方法，存储芯片和基于存储芯片互连的系统公开(公告)号：US20150293859A1
公开(公告)日：2015-10-15
申请号：US14751368
申请日：2015-06-26
Applicant: Huawei Technologies Co., Ltd.
Inventor： Yongbing Huang , Mingyu Chen , Yuan Ruan , Licheng Chen
CPC classification number: G06F12/1458 , G06F3/0622 , G06F3/0635 , G06F3/0683 , G06F13/1642 , G06F2212/1016 , G06F2212/1052 , G11C7/1003 , G11C7/1075
Abstract: A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present invention includes: receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present invention are mainly used in a process of processing a memory access request.
Abstract translation: 存储器访问处理方法基于与电子设备领域相关的存储器芯片互连，存储器芯片和系统，并且可以缩短处理存储器访问请求的时间延迟并提高系统带宽的利用率。 本发明的方法包括：由第一存储器芯片接收存储器访问请求; 并且如果第一存储器芯片不是与存储器访问请求对应的目标存储器芯片，则根据预配置的路由规则将存储器访问请求发送到与第一存储器芯片连接的下一个存储器芯片，直到目标存储器芯片对应 到存储器访问请求被确定。 本发明的实施例主要用于处理存储器访问请求的过程。
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