公开(公告)号：US10976956B2

公开(公告)日：2021-04-13

申请号：US16366325

申请日：2019-03-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Tianyue Lu ,  Mingyu Chen ,  Yuan Ruan ,  Wei Yang

IPC: G06F3/06 ,  G06F12/0873 ,  G06F16/903 ,  G06F13/14 ,  H04L12/801

Abstract: In a non-volatile memory (NVM) persistence method, a memory controller maintains a plurality of memory write instruction sets that are locked separately for persistence of write operations. A credit value for monitoring a quantity of completed write instructions is configured for each of the plurality of memory write instruction sets, and a credit value is also configured for each of a plurality of medium write instruction sets maintained by a medium controller and corresponding respectively to the memory write instruction sets. After a memory write instruction set is locked in response to a persistence query, the credit value of a corresponding medium write instruction set is used as means for the memory controller to determine whether the write instructions in the locked memory write instruction set have been completed by the medium controller.

公开(公告)号：US20190220224A1

公开(公告)日：2019-07-18

申请号：US16366325

申请日：2019-03-27

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Tianyue Lu ,  Mingyu Chen ,  Yuan Ruan ,  Wei Yang

IPC: G06F3/06 ,  G06F16/903

CPC classification number: G06F3/0656 ,  G06F3/0619 ,  G06F3/0679 ,  G06F12/0873 ,  G06F16/903

Abstract: In a non-volatile memory (NVM) persistence method, a memory controller maintains a plurality of memory write instruction sets that are locked separately for persistence of write operations. A credit value for monitoring a quantity of completed write instructions is configured for each of the plurality of memory write instruction sets, and a credit value is also configured for each of a plurality of medium write instruction sets maintained by a medium controller and corresponding respectively to the memory write instruction sets. After a memory write instruction set is locked in response to a persistence query, the credit value of a corresponding medium write instruction set is used as means for the memory controller to determine whether the write instructions in the locked memory write instruction set have been completed by the medium controller.

公开(公告)号：US20190196989A1

公开(公告)日：2019-06-27

申请号：US16289134

申请日：2019-02-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tianyue Lu ,  Yuan Ruan ,  Mingyu Chen ,  Shaojie Chen

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/372 ,  G06F3/06 ,  G06F9/30

CPC classification number: G06F13/1673 ,  G06F3/06 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0679 ,  G06F9/30101 ,  G06F13/1642 ,  G06F13/1668 ,  G06F13/18 ,  G06F13/372 ,  G11C7/1051 ,  G11C7/1063

Abstract: A storage system includes a memory controller and a memory device, and the memory device includes a medium controller, a memory, and a buffer. The medium controller is configured to write, into the buffer after receiving an access request, data requested by the access request. The memory controller is configured to send a query request to the medium controller after sending the access request to the medium controller, where the query request is used to query whether data has been written into the buffer. The medium controller is further configured to determine, based on the query request, whether data has been written into the buffer, and send the data that has been written into the buffer to the memory controller when there is data in the buffer.

公开(公告)号：US09898421B2

公开(公告)日：2018-02-20

申请号：US14751368

申请日：2015-06-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan ,  Licheng Chen

IPC: G06F12/02 ,  G06F12/14 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F12/1458 ,  G06F3/0622 ,  G06F3/0635 ,  G06F3/0683 ,  G06F13/1642 ,  G06F2212/1016 ,  G06F2212/1052 ,  G11C7/1003 ,  G11C7/1075

Abstract: A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present disclosure includes receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present disclosure are mainly used in a process of processing a memory access request.

公开(公告)号：US09785551B2

公开(公告)日：2017-10-10

申请号：US14953320

申请日：2015-11-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Licheng Chen ,  Zehan Cui

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0284 ,  G06F13/1605 ,  G06F13/1673 ,  G06F2212/1044 ,  G06F2212/2532

Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

公开(公告)号：US20160371198A1

公开(公告)日：2016-12-22

申请号：US15257506

申请日：2016-09-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Licheng Chen ,  Mingyu Chen

IPC: G06F12/1027 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/0811 ,  G06F12/0842

CPC classification number: G06F12/1027 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/6042 ,  G06F2212/651 ,  G06F2212/653 ,  G06F2212/657

Abstract: A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.

Abstract translation: 一种用于高速缓存地址的映射处理方法和装置，其中该方法包括获取对应于由处理核心发送的访问地址的物理地址，其中物理地址包括物理页号（PPN）和页偏移量， 地址到缓存地址，其中缓存地址包括缓存集索引1，缓存标签，高速缓存集索引2和高速缓存块偏移顺序，其中高速缓存集索引1具有高位位，高速缓存 将低位位置索引2一起形成缓存集索引，缓存集索引1落在PPN的范围内。 巨大页面PPN的PPN的一些位被映射到Cache的设置索引，使得可以由操作系统对这些位进行着色。

公开(公告)号：US20160085670A1

公开(公告)日：2016-03-24

申请号：US14953320

申请日：2015-11-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Licheng Chen ,  Zehan Cui

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0284 ,  G06F13/1605 ,  G06F13/1673 ,  G06F2212/1044 ,  G06F2212/2532

Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

Abstract translation: 本发明公开了一种存储器访问方法，缓冲器调度器和存储器模块，其可以在不改变存储器模块或存储器芯片的情况下支持多种应用场景。 该方法包括：接收用于存储器访问数据的操作请求消息，其中操作请求消息包括存储器访问数据的标签信息，存储器访问数据的操作信息和存储器访问数据的存储器地址; 并且根据存储器访问数据的标签信息，存储器访问数据的存储器地址和存储器访问数据的操作信息中的至少一个来执行对存储器访问数据的标签的操作和/或 存储器存储数据存储在存储器模块中。 本发明可应用于计算机领域。

公开(公告)号：US20150220135A1

公开(公告)日：2015-08-06

申请号：US14685272

申请日：2015-04-13

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan

IPC: G06F1/32

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/068 ,  G06F9/5016 ,  G06F9/5094 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/251 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154 ,  Y02D10/22 ,  Y02D50/20

Abstract: A method for reducing power consumption of a memory system and a memory controller are provided. The method for reducing power consumption of a memory system includes: determining whether a dynamic random access memory DRAM memory module with a low access frequency exists in a memory system; when a DRAM memory module with a low access frequency exists, transfer, according to a size of a working set in the memory system, page data that does not belong to the working set to a non-volatile memory NVM memory module, where the page data that does not belong to the working set is page data that does not need to be accessed when a process runs within preset time.

Abstract translation: 提供了一种用于降低存储器系统和存储器控制器的功耗的方法。 用于降低存储器系统的功耗的方法包括：确定存储系统中是否存在具有低存取频率的动态随机存取存储器DRAM存储器模块; 当存在具有低访问频率的DRAM存储器模块时，根据存储器系统中的工作集的大小将不属于工作集的页面数据传送到非易失性存储器NVM存储器模块，其中页面 不属于工作集的数据是当一个进程在预设时间内运行时不需要访问的页面数据。

公开(公告)号：US11237728B2

公开(公告)日：2022-02-01

申请号：US16744795

申请日：2020-01-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Mingyu Chen ,  Yao Liu ,  Yuan Ruan

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/02

Abstract: In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

公开(公告)号：US10318165B2

公开(公告)日：2019-06-11

申请号：US15357408

申请日：2016-11-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Fei Xia ,  Mingyu Chen ,  Dejun Jiang ,  Jin Xiong

IPC: G06F3/06 ,  G06F12/00 ,  G06F12/0868

Abstract: A data operating method, device, and system are provided. The method includes: receiving an operation instruction sent by a CPU; when the operation instruction is a read instruction, reading a first data block in the block device and returning to-be-read data in the first data block to the CPU; or when the operation instruction is a write instruction, writing, into a cache, to-be-written data indicated by the write instruction, and writing, into the block device, a second data block that includes the to-be-written data. The method is used to operate data in a block device.