公开(公告)号：US10552337B2

公开(公告)日：2020-02-04

申请号：US15343693

申请日：2016-11-04

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yao Liu ,  Yongbing Huang ,  Mingyu Chen ,  Zehan Cui ,  Licheng Chen ,  Yuan Ruan

IPC: G06F12/1027 ,  G06F3/06 ,  G06F12/1009

Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

公开(公告)号：US11237728B2

公开(公告)日：2022-02-01

申请号：US16744795

申请日：2020-01-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zehan Cui ,  Mingyu Chen ,  Yao Liu ,  Yuan Ruan

IPC: G06F3/06 ,  G06F12/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/02

Abstract: In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

公开(公告)号：US09927860B2

公开(公告)日：2018-03-27

申请号：US14685272

申请日：2015-04-13

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan

IPC: G06F1/32 ,  G06F9/50 ,  G06F12/06 ,  G06F3/06

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/068 ,  G06F9/5016 ,  G06F9/5094 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/251 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154 ,  Y02D10/22 ,  Y02D50/20

Abstract: A method for reducing power consumption of a memory system and a memory controller are provided. The method for reducing power consumption of a memory system includes: determining whether a dynamic random access memory DRAM memory module with a low access frequency exists in a memory system; when a DRAM memory module with a low access frequency exists, transfer, according to a size of a working set in the memory system, page data that does not belong to the working set to a non-volatile memory NVM memory module, where the page data that does not belong to the working set is page data that does not need to be accessed when a process runs within preset time.

公开(公告)号：US20160055898A1

公开(公告)日：2016-02-25

申请号：US14922973

申请日：2015-10-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuan Ruan ,  Mingyu Chen

IPC: G11C11/406 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/40607 ,  G06F12/02 ,  G06F13/1673 ,  G11C7/1063 ,  G11C7/1072

Abstract: A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delays a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem, reduces the memory access time.

Abstract translation: 第一级缓冲器芯片根据预先设定的映射关系对目标第二级缓冲器芯片进行门控，第一片选信号和第一高位地址信号，并转发存储器存取指令和从 内存控制器到目标二级缓冲芯片。 目标第二级缓冲器芯片根据第二芯片选择信号和通过延迟第二高阶地址信号获得的延迟地址信号来确定目标存储器模块，根据低阶地址信号确定目标存储器芯片，获取目标 根据存储器访问指令从目标存储器芯片获取数据，并将目标数据返回到存储器控制器。 系统存储器的级联方式更改为树形拓扑形式，避免了协议转换问题，减少了存储器访问时间。

公开(公告)号：US20150220448A1

公开(公告)日：2015-08-06

申请号：US14687607

申请日：2015-04-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyang Chen ,  Mingyu Chen ,  Zehan Cui ,  Yuan Ruan

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/35

CPC classification number: H03M7/6011 ,  G06F9/30138 ,  G06F9/35 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/385 ,  G06F17/30153 ,  G06F2212/6032 ,  G06F2212/657

Abstract: An address compression method, an address decompression method, a compressor, and a decompressor, which can improve an address compression ratio. The address compression method includes after a compressor receives multiple operation request messages that are sent by a first processor, determining, according to an address feature formed by address information carried in all operation request messages that have a same stream number, a compression algorithm corresponding to the operation request messages that have a same stream number; and then compressing, according to the determined compression algorithm, addresses carried in the operation request messages that have a same stream number. The present invention is applicable to the computer field.

Abstract translation: 地址压缩方法，地址解压缩方法，压缩器和解压缩器，可以提高地址压缩比。 地址压缩方法包括在压缩机接收到由第一处理器发送的多个操作请求消息之后，根据由具有相同流号的所有操作请求消息中携带的地址信息形成的地址特征，确定与 具有相同流号码的操作请求消息; 然后根据确定的压缩算法压缩具有相同流号的操作请求消息中承载的地址。 本发明可应用于计算机领域。

公开(公告)号：US10545672B2

公开(公告)日：2020-01-28

申请号：US15788990

申请日：2017-10-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zehan Cui ,  Mingyu Chen ,  Yao Liu ,  Yuan Ruan

IPC: G06F3/06

Abstract: A method for accessing an extended memory, a device, and a system are disclosed. According to the method, after receiving a first memory access requests from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

公开(公告)号：US20180039424A1

公开(公告)日：2018-02-08

申请号：US15788990

申请日：2017-10-20

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Zehan Cui ,  Mingyu Chen ,  Yao Liu ,  Yuan Ruan

IPC: G06F3/06

Abstract: A method for accessing an extended memory, a device, and a system are disclosed. According to the method, after receiving a first memory access requests from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

公开(公告)号：US09870327B2

公开(公告)日：2018-01-16

申请号：US14335029

申请日：2014-07-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyu Chen ,  Yuan Ruan ,  Zehan Cui ,  Licheng Chen ,  Yongbing Huang ,  Mingyang Chen

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4239

Abstract: A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

公开(公告)号：US09812186B2

公开(公告)日：2017-11-07

申请号：US14922973

申请日：2015-10-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuan Ruan ,  Mingyu Chen

IPC: G11C11/406 ,  G06F12/02 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/40607 ,  G06F12/02 ,  G06F13/1673 ,  G11C7/1063 ,  G11C7/1072

Abstract: A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delay processing on a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem and reduces the memory access time.

公开(公告)号：US09495304B2

公开(公告)日：2016-11-15

申请号：US14687607

申请日：2015-04-15

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyang Chen ,  Mingyu Chen ,  Zehan Cui ,  Yuan Ruan

IPC: G06F12/00 ,  G06F12/10 ,  G06F9/30 ,  G06F9/35 ,  G06F13/38 ,  G06F17/30

CPC classification number: H03M7/6011 ,  G06F9/30138 ,  G06F9/35 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/385 ,  G06F17/30153 ,  G06F2212/6032 ,  G06F2212/657

Abstract: An address compression method, an address decompression method, a compressor, and a decompressor are disclosed, wherein the address compression method includes after a compressor receives multiple operation request messages that are sent by a first processor, determining, according to an address feature formed by address information carried in all operation request messages that have a same stream number, a compression algorithm corresponding to the operation request messages that have a same stream number; and then compressing, according to the determined compression algorithm, addresses carried in the operation request messages that have a same stream number. The present invention is applicable to the computer field.

Abstract translation: 公开了一种地址压缩方法，地址解压缩方法，压缩器和解压缩器，其中地址压缩方法包括在压缩器接收到由第一处理器发送的多个操作请求消息之后，根据由 在具有相同流号的所有操作请求消息中携带的地址信息，与具有相同流号的操作请求消息相对应的压缩算法; 然后根据确定的压缩算法压缩具有相同流号的操作请求消息中承载的地址。 本发明可应用于计算机领域。