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    DATA RELAY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME
    37.
    发明申请
    DATA RELAY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME 失效
    数据继电器和半导体集成电路

    公开(公告)号：US20090092215A1

    公开(公告)日：2009-04-09

    申请号：US12038616

    申请日：2008-02-27

    申请人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    发明人： Ic-Su Oh ,  Kun-Woo Park ,  Yong-Ju Kim ,  Hee-Woong Song ,  Hyung-Soo Kim ,  Tae-Jin Hwang ,  Hae-Rang Choi ,  Ji-Wang Lee

    IPC分类号： H04L7/00

    CPC分类号： H03K5/135 ,  H03L7/06

    摘要： A data relay apparatus according to one embodiment described herein can include a phase detection unit that can detect a phase difference between a clock output from a transmitter and a clock output from a receiver, and generate a plurality of phase detection signals, a data relay control unit that can distinguish a difference in clock timing between the clocks of the transmitter and the receiver in response to the plurality of phase detection signals, and output a relay data selection signal and a relay control clock, and a data relay unit that can transmit data output from the receiver to the transmitter in response to the relay data selection signal and the relay control clock.

    摘要翻译： 根据本文所述的一个实施例的数据中继装置可以包括相位检测单元，其可以检测从发送器输出的时钟与从接收器输出的时钟之间的相位差，并且生成多个相位检测信号，数据中继控制 单元，其可以响应于所述多个相位检测信号来区分发射机和接收机的时钟之间的时钟定时的差异，并且输出中继数据选择信号和中继控制时钟，以及可以发送数据的数据中继单元 响应于继电器数据选择信号和继电器控制时钟从接收器输出到发送器。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME
    39.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME 有权
    半导体集成电路及其驱动方法

    公开(公告)号：US20130099838A1

    公开(公告)日：2013-04-25

    申请号：US13334241

    申请日：2011-12-22

    申请人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    发明人： Yong-Ju Kim ,  Dae-Han Kwon ,  Hae-Rang Choi ,  Jae-Min Jang

    IPC分类号： H03L7/095

    CPC分类号： H03L7/0814 ,  G11C7/222 ,  G11C11/40 ,  G11C29/023 ,  G11C2029/0409

    摘要： A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

    摘要翻译： 半导体集成电路包括：延迟锁定环（DLL），被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号，其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器，被配置为响应于源时钟信号和从DLL提供的多个控制信号，基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

    Phase locked loop
    40.
    发明授权
    Phase locked loop 有权
    锁相环

    公开(公告)号：US08410836B2

    公开(公告)日：2013-04-02

    申请号：US12916901

    申请日：2010-11-01

    申请人： Hae-Rang Choi ,  Yong-Ju Kim ,  Jae-Min Jang

    发明人： Hae-Rang Choi ,  Yong-Ju Kim ,  Jae-Min Jang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/14 ,  H03L7/113

    摘要： A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.

    摘要翻译： 锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测 结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。