公开(公告)号：US07317657B2

公开(公告)日：2008-01-08

申请号：US11319754

申请日：2005-12-29

Applicant: Martin Brox ,  Helmut Fischer

Inventor： Martin Brox ,  Helmut Fischer

IPC: G11C8/00

CPC classification number: G11C11/4076 ,  G11C7/1045 ,  G11C7/22

Abstract: The invention relates to a semiconductor memory device, a system with a semiconductor memory device, and a method for operating a semiconductor memory device, comprising the steps of reading out a data value, in particular a CAS latency time data value (CL) stored in a memory; activating or deactivating a device provided on said semiconductor memory device in support of a high speed operation, as a function of the data value (CL) stored.

Abstract translation: 本发明涉及半导体存储器件，具有半导体存储器件的系统和用于操作半导体存储器件的方法，包括以下步骤：读出数据值，特别是存储在存储器中的CAS等待时间数据值（CL） 记忆 作为存储的数据值（CL）的函数，激活或去激活设置在所述半导体存储器件上的设备以支持高速操作。

公开(公告)号：US07076021B2

公开(公告)日：2006-07-11

申请号：US10739673

申请日：2003-12-17

Applicant: Helmut Fischer ,  Volker Rössiger

Inventor： Helmut Fischer ,  Volker Rössiger

IPC: G01N23/223

CPC classification number: G01B15/02 ,  G01N23/223 ,  G01N2223/076

Abstract: An apparatus for measurement of the thickness of thin layers by means of X-rays using an X-ray tube which emits X-rays which are directed at a layer to be measured, has at least one aperture apparatus arranged between the X-ray tube and the layer to be measured. The apparatus includes an area absorbing X-rays and an aperture opening. At least one aperture opening in the aperture apparatus has a geometric shape which, seen in the beam direction, projects an area which at least in places is matched to the geometry of the layer to be measured.

Abstract translation: 一种利用X射线管测量薄层厚度的装置，该X射线管发射指向被测层的X射线，具有至少一个孔径装置，其设置在X射线管 和要测量的层。 该装置包括吸收X射线和孔径开口的区域。 开口装置中的至少一个开口开口具有几何形状，其在波束方向上看到至少在与被测量层的几何形状匹配的区域上突出。

公开(公告)号：US07008810B2

公开(公告)日：2006-03-07

申请号：US10804514

申请日：2004-03-19

Applicant: Christine Höss ,  Andreas Weimar ,  Andreas Leber ,  Alfred Lell ,  Helmut Fischer ,  Volker Harle

Inventor： Christine Höss ,  Andreas Weimar ,  Andreas Leber ,  Alfred Lell ,  Helmut Fischer ,  Volker Harle

IPC: H01L21/00

CPC classification number: H01L33/005 ,  H01S5/021 ,  H01S5/2081 ,  H01S5/22 ,  H01S5/2214 ,  H01S5/32341 ,  Y10S438/951

Abstract: A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for definition of the mesa or ridge dimensions. The sacrificial layer (4) and of the layer or layer sequence are removed so that the mesa or ridge structure is formed in the layer or layer sequence. A part of the sacrificial layer (4) is selectively removed from the side areas thereof which have been uncovered in the previous step, so that a sacrificial layer remains which is narrower in comparison with a layer that has remained above the sacrificial layer as seen from the layer or layer sequence. A coating is applied at least to the sidewalls of the structure produced in the previous steps so that the side areas of the residual sacrificial layer are not completely overformed by the coating material. The sacrificial layer (4) is removed so that the layer that has remained above the sacrificial layer as seen from the layer or layer sequence is lifted off. A method is also disclosed for fabricating at least one gain-controlled laser diode in a layer sequence, in which method steps analogous to those described above are employed.

Abstract translation: 一种用于在层或层序列中制造至少一个台面或脊状结构的方法，其中牺牲层（4）被施加并在层或层序列上形成图案。 掩模层被施加和图案化在牺牲层上方以定义台面或脊尺寸。 去除牺牲层（4）和层或层序列，使得台层或脊结构以层或层序列形成。 牺牲层（4）的一部分从其前面的步骤中未被覆盖的侧面区域选择性地去除，从而与牺牲层上方的层相比较，牺牲层保持较窄，如从 层或层序列。 至少将涂层施加到在前述步骤中制造的结构的侧壁上，使得残余牺牲层的侧面区域不会被涂层材料完全覆盖。 去除牺牲层（4），使得从层或层序列看到的保留在牺牲层上方的层被提升。 还公开了一种用于在层序列中制造至少一个增益控制的激光二极管的方法，其中采用与上述类似的方法步骤。

公开(公告)号：US06859411B2

公开(公告)日：2005-02-22

申请号：US10623831

申请日：2003-07-21

Applicant: Johann Pfeiffer ,  Helmut Fischer

Inventor： Johann Pfeiffer ,  Helmut Fischer

IPC: G11C11/408 ,  G11C11/4097 ,  G11C8/00

CPC classification number: G11C11/4097 ,  G11C11/4087

Abstract: A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.

Abstract translation: 在动态存储器电路上执行用于写入和读取数据的方法。 存储器电路具有可通过字线和位线寻址的存储单元。 在使用特定地址寻址存储区域的情况下，字线被激活。 字线具有多个相互分离的字线部分。 通过位线，在与特定地址进行寻址的情况下，并行地将第一数量的数据写入由地址寻址的存储器单元，或者可以从地址寻址的存储单元读取第一数据数。 在使用特定地址进行寻址的情况下，只有一部分字线部分被激活，以便仅连接到字线的存储器单元的一部分被并行地并行地并行地读取。

公开(公告)号：US06788228B2

公开(公告)日：2004-09-07

申请号：US10364014

申请日：2003-02-10

Applicant: Alan Morgan ,  Helmut Fischer

Inventor： Alan Morgan ,  Helmut Fischer

IPC: H03M700

CPC classification number: G11C29/781 ,  G11C29/787 ,  G11C29/812

Abstract: An addressing device selects an element from a set of N≦2K regular elements or alternatively from a set of R

Abstract translation: 寻址装置从一组N <= 2KK个常规元素中选择一个元素，或者根据一个R-N个冗余元素来选择一个元素，这取决于一个K位输入地址， N解码器，并且其解析常规元素。 对于每个冗余元件，提供旁路电路，并且在每种情况下都具有用于提供通过选择性破坏可编程的K个参考位或者通过选择性地引入导电链路以将比较器件设置为所选择的标识的参考位发射器 地址。 如果相关地址被识别，则旁路电路解决分配给它的冗余元件，同时关闭1-out-N解码器，只要它是敏感的。 对于其敏化，每个双稳态电路检查参考位的M

公开(公告)号：US06777930B2

公开(公告)日：2004-08-17

申请号：US09818036

申请日：2001-03-26

Applicant: Helmut Fischer

Inventor： Helmut Fischer

IPC: G01B706

CPC classification number: G01B7/105

Abstract: A method for the nondestructive measurement of the thickness of thin layers having a probe, having a first coil device on an inner core, the geometrical center of which coil device and the geometrical center of at least one second coil device coincide, the at least one second coil device partially surrounding the first coil device, and an evaluation unit, to which signals of the coil devices are emitted during a measurement for ascertaining the layer thickness. A circuit is provided, by which the first and the at least one second coil devices are excited sequentially during a measurement.

Abstract translation: 一种用于非破坏性测量具有探针的薄层的厚度的方法，所述探针在内芯上具有第一线圈装置，所述线圈装置的几何中心和至少一个第二线圈装置的几何中心重合，所述至少一个 部分地围绕第一线圈装置的第二线圈装置以及评估单元，在测量期间发射线圈装置的信号以确定层厚度。 提供一种电路，通过该电路，在测量期间第一和至少一个第二线圈装置依次被激励。

公开(公告)号：US06711085B2

公开(公告)日：2004-03-23

申请号：US10266190

申请日：2002-10-07

Applicant: Helmut Fischer ,  Johann Pfeiffer

Inventor： Helmut Fischer ,  Johann Pfeiffer

IPC: G11C800

CPC classification number: G11C11/4097 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4094

Abstract: A digital memory circuit contains a plurality of areas each having memory cells disposed in matrix form in rows and columns. The columns of each memory area is subdivided into a plurality of adjacent groups which each form a segment. For each segment, provision is made of a separate set of two-conductor local data lines which lead via line switches to two-conductor master data lines common to all the memory areas. Furthermore, precharge devices are provided in order to equalize the potentials of the conductors of the local data lines and the conductors of the master data lines, the equalization potential for the local data lines being different than the equalization potential for the master data lines. A line switch control device provides for closing only of the line switches on those local data lines which belong to the segment in which a write or read mode takes place.

Abstract translation: 数字存储器电路包括多个区域，每个区域具有以行和列的矩阵形式设置的存储单元。 每个存储器区域的列被细分成多个相邻的组，每个组形成一个段。 对于每个段，提供一组单独的双导体本地数据线，其通过线路开关导通到所有存储区域共有的双导线主数据线。 此外，提供预充电装置以便均衡本地数据线的导体和主数据线的导体的电位，本地数据线的均衡电位与主数据线的均衡电位不同。 线路开关控制装置提供仅关闭属于发生写入或读取模式的段的那些本地数据线上的线路交换机。

公开(公告)号：US06635947B2

公开(公告)日：2003-10-21

申请号：US09934979

申请日：2001-08-21

Applicant: Alexander Benedix ,  Georg Braun ,  Helmut Fischer ,  Bernd Klehn ,  Sebastian Kuhne

Inventor： Alexander Benedix ,  Georg Braun ,  Helmut Fischer ,  Bernd Klehn ,  Sebastian Kuhne

IPC: H01L2900

CPC classification number: G11C11/16 ,  H01L43/08

Abstract: A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one another is described. The conductive layers are configured in such a way that they form a coil-type structure around a central region, in which giant magnetic resistance materials can be provided.

公开(公告)号：US06530872B2

公开(公告)日：2003-03-11

申请号：US10066640

申请日：2002-02-06

Applicant: Peter Frehland ,  Helmut Fischer

Inventor： Peter Frehland ,  Helmut Fischer

IPC: B04B906

CPC classification number: B04B5/005 ,  B04B9/12 ,  F01M2013/0422

Abstract: A centrifuge rotor for a free jet centrifuge for cleaning lubricating oil of an internal combustion engine. The rotor has an inlet, at least one drive nozzle outlet, and a sediment deposition surface interiorly in the rotor. A bearing is provided for rotatably mounting the rotor in a surrounding housing where the bearing includes a friction bearing which simultaneously forms the rotor inlet and a roller bearing which is receivable in a bearing receptacle formed in the surrounding housing. The roller bearing is sealed off from the rotor interior.

Abstract translation: 一种用于清洁内燃机润滑油的自由喷射离心机的离心机转子。 转子具有入口，至少一个驱动喷嘴出口和内部在转子中的沉积物沉积表面。 提供一种用于将转子可旋转地安装在周围壳体中的轴承，其中轴承包括同时形成转子入口的摩擦轴承和可接收在形成于周围壳体中的轴承座中的滚子轴承。 滚子轴承与转子内部密封。

公开(公告)号：US06477099B2

公开(公告)日：2002-11-05

申请号：US09761815

申请日：2001-01-16

Applicant: Helmut Fischer ,  Sebastian Kuhne ,  Thoai-Thai Le

Inventor： Helmut Fischer ,  Sebastian Kuhne ,  Thoai-Thai Le

IPC: G11C702

CPC classification number: H03F3/45183

Abstract: An integrated circuit has a differential amplifier in a basic circuit having two input transistors, a load element and a power source. The power source has an N-type channel MOS transistor whose controlled path is connected to the input transistors and to a supply terminal of the power source. A control terminal of the transistor is connected to a potential that is positive with respect to a reference potential. The supply terminal of the power source is connected to a potential which is negative with respect to the reference potential and which is made available by a voltage source for switching off cell field transistors of a DRAM memory. The gate-source voltage that is increased in this way improves the behavior of the circuit with respect to fluctuations in potential and permits more favorable dimensioning of the transistor.

Abstract translation: 集成电路在具有两个输入晶体管，负载元件和电源的基本电路中具有差分放大器。 电源具有N型沟道MOS晶体管，其受控路径连接到输入晶体管和电源的供电端子。 晶体管的控制端子连接到相对于参考电位为正的电位。 电源的供电端子连接到相对于参考电位为负的电位，并且由用于关断DRAM存储器的单元场晶体管的电压源可用。 以这种方式增加的栅极 - 源极电压改善了电路相对于电位波动的行为，并且允许晶体管的更有利的尺寸。