公开(公告)号：US4987463A

公开(公告)日：1991-01-22

申请号：US399099

申请日：1989-08-28

申请人： Herbert Goronkin ,  Saied N. Tehrani

发明人： Herbert Goronkin ,  Saied N. Tehrani

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/10 ,  H01L29/32 ,  H01L29/778

CPC分类号： H01L29/1075 ,  H01L29/32

摘要： A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

公开(公告)号：US5482875A

公开(公告)日：1996-01-09

申请号：US229266

申请日：1994-04-18

申请人： Rimantas L. Vaitkus ,  Saied N. Tehrani ,  Vijay K. Nair ,  Herbert Goronkin

发明人： Rimantas L. Vaitkus ,  Saied N. Tehrani ,  Vijay K. Nair ,  Herbert Goronkin

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/08 ,  H01L29/10 ,  H01L29/778 ,  H01L29/80 ,  H01L21/335

CPC分类号： H01L29/7783 ,  H01L29/0891 ,  H01L29/1029 ,  Y10S148/072

摘要： A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.

摘要翻译： 低功率异质结场效应晶体管（10,30,50,60）能够以低漏电流工作，同时具有低的互调失真。 在栅极（24,41,69）和漏极（25,46,65）之间形成沟道限制区（9,38,51）。 信道限制区域（9,38,51）耗尽信道层（13,33），从而限制信道并降低漏极饱和电流。 通道限制区域（9,38,51）可以用于设置所需的漏极饱和电流，使得相对于栅极 - 源极电压的跨导的二次导数近似为零，并且跨导的第一导数相对于 栅极源极电压大约在所需工作点处的相对最大值。

公开(公告)号：US5804458A

公开(公告)日：1998-09-08

申请号：US766076

申请日：1996-12-16

申请人： Saied N. Tehrani ,  Mark Durlam ,  Herbert Goronkin

发明人： Saied N. Tehrani ,  Mark Durlam ,  Herbert Goronkin

IPC分类号： H01L27/115 ,  H01L21/70

CPC分类号： H01L27/115 ,  H01L27/222 ,  H01L43/12

摘要： A method of fabricating a plurality of spaced apart submicron memory cells is disclosed, including the steps of depositing a magnetoresistive system on a substrate formation, depositing and patterning a first layer of material to form sidewalls, and depositing a second, selectively etchable, layer of material on the first layer of material, etching the second layer of material to define spacers on the sidewalls of the first layer of material, etching the magnetoresistive system, using the spacers as a mask, to define a plurality of spaced apart submicron magnetic memory cells, and depositing electrical contacts on the plurality of spaced apart submicron magnetic memory cells.

摘要翻译： 公开了一种制造多个间隔开的亚微米存储器单元的方法，包括以下步骤：在衬底形成上沉积磁阻系统，沉积和图形化第一材料层以形成侧壁，以及沉积第二层可选择的可蚀刻的 材料在第一层材料上蚀刻第二层材料以在第一材料层的侧壁上限定间隔物，使用间隔物作为掩模蚀刻磁阻系统以限定多个间隔开的亚微米磁存储器单元 并且在多个间隔开的亚微米磁存储器单元上沉积电触点。

公开(公告)号：US5742082A

公开(公告)日：1998-04-21

申请号：US753312

申请日：1996-11-22

申请人： Saied N. Tehrani ,  Jenn-Hwa Huang ,  Herbert Goronkin ,  Ernest Schirmann ,  Marino J. Martinez

发明人： Saied N. Tehrani ,  Jenn-Hwa Huang ,  Herbert Goronkin ,  Ernest Schirmann ,  Marino J. Martinez

IPC分类号： H01L21/338 ,  H01L29/10 ,  H01L29/812 ,  H01L29/80

CPC分类号： H01L29/66863 ,  H01L29/1075 ,  H01L29/8128

摘要： A stable FET including a substrate structure with a doped layer formed as a portion of the substrate structure and defining an electrically conductive shielding region adjacent a surface of the substrate structure. A channel region is positioned on the shielding region and includes a plurality of epitaxial layers grown on the surface of the substrate structure in overlying relationship to the doped layer. A drain and a source are positioned on the channel region in spaced relationship from each other with a gate positioned in overlying relationship on the channel region between the drain and source. An externally accessible electrical contact is connected to the shielding region and to the source region to provide a path for the removal of internally generated charges, such as holes.

摘要翻译： 一种稳定的FET，其包括具有掺杂层的衬底结构，所述掺杂层形成为所述衬底结构的一部分并且限定邻近所述衬底结构的表面的导电屏蔽区域。 通道区域位于屏蔽区域上，并且包括以与掺杂层相重叠的方式在衬底结构的表面上生长的多个外延层。 漏极和源极以彼此间隔开的关系定位在沟道区上，栅极位于漏极和源极之间的沟道区上的上限关系。 外部可接触的电触点连接到屏蔽区域和源极区域，以提供用于去除内部产生的电荷（例如孔）的路径。

公开(公告)号：US5732016A

公开(公告)日：1998-03-24

申请号：US674387

申请日：1996-07-02

申请人： Eugene Chen ,  Saied N. Tehrani ,  Herbert Goronkin

发明人： Eugene Chen ,  Saied N. Tehrani ,  Herbert Goronkin

IPC分类号： H01L43/08 ,  G11C11/14 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  G11C11/00

CPC分类号： G11C11/14 ,  H01L27/222 ,  H01L43/08

摘要： A magnetic random access memory (MRAM) cell structure (10) with a portion of giant magnetoresistive (GMR) material (11), around which single or multiple word line (12) is wound, is provided. Magnetic field generated by word current (13, 14) superimposed in portion of GMR material (11) so that a total strength of magnetic field increases proportionally. The same word current is passed through the portion of GMR material (11) multiple times, thus producing equivalent word field by many times as large word current in a conventional MRAM cell.

摘要翻译： 提供具有卷绕单字或多字线（12）的巨磁阻（GMR）材料（11）的一部分的磁随机存取存储器（MRAM）单元结构（10）。 由字电流（13,14）产生的磁场叠加在GMR材料（11）的一部分中，使得磁场的总强度成比例地增加。 相同的字电流多次通过GMR材料（11）的部分，从而在常规MRAM单元中产生大字电流多次的等效字场。

公开(公告)号：US5304825A

公开(公告)日：1994-04-19

申请号：US932526

申请日：1992-08-20

申请人： Rimantas L. Vaitkus ,  Saied N. Tehrani ,  Vijay K. Nair ,  Herbert Goronkin

发明人： Rimantas L. Vaitkus ,  Saied N. Tehrani ,  Vijay K. Nair ,  Herbert Goronkin

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/08 ,  H01L29/10 ,  H01L29/778 ,  H01L29/80 ,  H01L31/072 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109

CPC分类号： H01L29/7783 ,  H01L29/0891 ,  H01L29/1029 ,  Y10S148/072

摘要： A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.

摘要翻译： 低功率异质结场效应晶体管（10,30,50,60）能够以低漏电流工作，同时具有低的互调失真。 在栅极（24,41,69）和漏极（25,46,65）之间形成沟道限制区（9,38,51）。 信道限制区域（9,38,51）耗尽信道层（13,33），从而限制信道并降低漏极饱和电流。 通道限制区域（9,38,51）可以用于设置所需的漏极饱和电流，使得相对于栅极 - 源极电压的跨导的二次导数近似为零，并且跨导的第一导数相对于 栅极源极电压大约在所需工作点处的相对最大值。

公开(公告)号：US5172384A

公开(公告)日：1992-12-15

申请号：US695062

申请日：1991-05-03

申请人： Herbert Goronkin ,  Michael S. Lebby ,  Saied N. Tehrani

发明人： Herbert Goronkin ,  Michael S. Lebby ,  Saied N. Tehrani

IPC分类号： G02F1/017 ,  H01L33/00 ,  H01S5/34

CPC分类号： H01S5/34 ,  B82Y20/00 ,  G02F1/017 ,  H01S5/3403

摘要： A thin layer, typically a monolayer, of a small band gap material (37) is inserted into the active layer (14) of a quantum well semiconductor device (36, 51). The band gap of the thin layer (37) is smaller than the band gap of the material in the active layer (14), thereby shifting carrier concentrations in the quantum well (26d, 26e, 26h, 26n) of the active layer (14) toward the thin layer (37). This shift increases alignment between the electron wave function (42, 54) and the hole wave function (44, 57) in the quantum well (26d, 26e, 26h, 26n) which increases the probability of stimulated photon emissions thereby reducing the threshold current and threshold voltage of the quantum well semiconductor device (36, 51).

摘要翻译： 将小带隙材料（37）的薄层（通常为单层）插入量子阱半导体器件（36,51）的有源层（14）中。 薄层（37）的带隙比有源层（14）中的材料的带隙小，从而使有源层（14）的量子阱（26d，26e，26h，26n）中的载流子浓度移位 ）朝向薄层（37）。 这种移动增加了量子阱（26d，26e，26h，26n）中的电子波函数（42,54）和空穴波函数（44,57）之间的对准，这增加了被激发的光子发射的概率，从而降低阈值电流 和量子阱半导体器件（36,51）的阈值电压。

公开(公告)号：US5141879A

公开(公告)日：1992-08-25

申请号：US563128

申请日：1990-08-06

申请人： Herbert Goronkin ,  Saied N. Tehrani

发明人： Herbert Goronkin ,  Saied N. Tehrani

IPC分类号： H01L29/10 ,  H01L29/32

CPC分类号： H01L29/1075 ,  H01L29/32 ,  Y10S438/904

摘要： A FET having a high trap concentration interface layer and method of fabrication includes a semi-insulating gallium arsenide substrate having a high trap concentration interface layer formed therein. An non-intentionally doped buffer layer, also comprised of gallium arsenide, is then formed on the interface layer and is followed by the formation of a doped aluminum gallium arsenide layer thereon. A source, a gate and a drain are then formed on the FET layers. The FET and method disclosed herein are especially applicable for low current (5-1000 microamp) operation of microwave low-noise FETs.

摘要翻译： 具有高陷阱浓度界面层的FET和制造方法包括其中形成有高陷阱浓度界面层的半绝缘砷化镓衬底。 然后在界面层上形成也由砷化镓组成的非有意掺杂的缓冲层，随后在其上形成掺杂的砷化镓铝层。 然后在FET层上形成源极，栅极和漏极。 本文公开的FET和方法特别适用于微波低噪声FET的低电流（5-1000微安）操作。

公开(公告)号：US5818316A

公开(公告)日：1998-10-06

申请号：US892641

申请日：1997-07-15

申请人： Jun Shen ,  Saied N. Tehrani ,  Eugene Chen

发明人： Jun Shen ,  Saied N. Tehrani ,  Eugene Chen

IPC分类号： G11C11/50 ,  G11C23/00 ,  H01H51/22

CPC分类号： G11C11/50 ,  G11C23/00

摘要： A nonvolatile programmable switch includes first and second magnetizable conductors having first and second ends, respectively, each of which is a north or south pole. The ends are mounted for relative movement between a first position in which they are in contact and a second position in which they are insulated from each other. The first conductor is permanently magnetized and the second conductor is switchable in response to a magnetic field applied thereto. Programming means are associated with the second conductor for switchably magnetizing the second conductor so that the second end is alternatively a north or south pole. The first and second ends are held in the first position by magnetic attraction and in the second position by magnetic repulsion.

摘要翻译： 非易失性可编程开关包括分别具有第一和第二端的第一和第二可磁化导体，其中每一个是北极或南极。 端部被安装成在它们接触的第一位置和彼此绝缘的第二位置之间进行相对运动。 第一导体被永久磁化，并且第二导体响应于施加到其上的磁场而可切换。 编程装置与第二导体相关联，用于可切换地磁化第二导体，使得第二端可选地是北极或南极。 第一和第二端通过磁吸引力保持在第一位置，并且在第二位置通过磁力排斥保持。

公开(公告)号：US5659180A

公开(公告)日：1997-08-19

申请号：US556686

申请日：1995-11-13

申请人： Jun Shen ,  Raymond K. Tsui ,  Saied N. Tehrani ,  Herb Goronkin

发明人： Jun Shen ,  Raymond K. Tsui ,  Saied N. Tehrani ,  Herb Goronkin

IPC分类号： H01L29/88 ,  H01L29/06

CPC分类号： H01L29/88

摘要： A heterojunction tunnel diode with first and second barrier layers, the first barrier layer including aluminum antimonide arsenide. A quantum well formation is sandwiched between the first and second barrier layers, and includes first and second quantum well layers with a barrier layer sandwiched therebetween, the first quantum well layer being adjacent the first barrier layer. The first quantum well layer is gallium antimonide arsenide which produces a peak in hole accumulations therein. The second quantum well layer produces a peak in electron accumulations therein. A monolayer of gallium antimonide is sandwiched in the first quantum well layer at the peak in hole accumulations and a monolayer of indium arsenide is sandwiched in the second quantum well layer at the peak in electron accumulations.

摘要翻译： 一种具有第一和第二阻挡层的异质结隧道二极管，所述第一阻挡层包括锑化砷化砷。 量子阱形成夹在第一和第二阻挡层之间，并且包括夹在其间的阻挡层的第一和第二量子阱层，第一量子阱层与第一阻挡层相邻。 第一量子阱层是在其中产生孔积聚的峰值的锑化锑砷化物。 第二量子阱层在其中产生电子积聚中的峰。 单层的锑化镓被夹在第一量子阱层中，在空穴积聚的峰值处，并且在电子积累的峰值处将第二量子阱层中的单层砷化铟夹在第二量子阱层中。