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    Method to improve branch prediction latency
    32.
    发明授权
    Method to improve branch prediction latency 有权
    提高分支预测延迟的方法

    公开(公告)号：US08151096B2

    公开(公告)日：2012-04-03

    申请号：US12187126

    申请日：2008-08-06

    Applicant: Herbert Hum ,  Hongliang Gao

    Inventor： Herbert Hum ,  Hongliang Gao

    IPC: G06F7/38 ,  G06F9/00 ,  G06F9/44

    CPC classification number: G06F9/3844

    Abstract: An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction in a program order. The prediction can also based on a branch history value with respect to the previous branch instruction and one or more previous branch predictions.

    Abstract translation: 至少部分地基于先前分支指令的地址生成指令的分支预测的装置，其中先前指令在程序顺序中指令之前。 预测还可以基于相对于先前分支指令的分支历史值和一个或多个先前分支预测。

    System and method for reservation station load dependency matrix
    33.
    发明授权
    System and method for reservation station load dependency matrix 有权
    保留站负载依赖矩阵的系统和方法

    公开(公告)号：US07958336B2

    公开(公告)日：2011-06-07

    申请号：US12164666

    申请日：2008-06-30

    Applicant: Sagi Lahav ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    Inventor： Sagi Lahav ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    IPC: G06F9/30

    CPC classification number: G06F9/3838 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3859

    Abstract: A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

    Abstract translation: 设备和方法可以获取用于执行的指令或微操作。 可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。 可以存储对应于第一指令所依赖的每个源值的值。 可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。 可以在与指令相关联的存储值表示满足依赖性之后执行指令。

    METHOD TO IMPROVE BRANCH PREDICTION LATENCY
    34.
    发明申请
    METHOD TO IMPROVE BRANCH PREDICTION LATENCY 有权
    改进分支预测延迟的方法

    公开(公告)号：US20100037036A1

    公开(公告)日：2010-02-11

    申请号：US12187126

    申请日：2008-08-06

    Applicant: Herbert Hum ,  Hongliang Gao

    Inventor： Herbert Hum ,  Hongliang Gao

    IPC: G06F9/38 ,  G06F9/312

    CPC classification number: G06F9/3844

    Abstract: An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction in a program order. The prediction can also based on a branch history value with respect to the previous branch instruction and one or more previous branch predictions.

    Abstract translation: 至少部分地基于先前分支指令的地址生成指令的分支预测的装置，其中先前指令在程序顺序中指令之前。 预测还可以基于相对于先前分支指令的分支历史值和一个或多个先前分支预测。

    Software constructed stands for execution on a multi-core architecture
    35.
    发明申请
    Software constructed stands for execution on a multi-core architecture 有权
    构建的软件代表在多核架构上执行

    公开(公告)号：US20090077360A1

    公开(公告)日：2009-03-19

    申请号：US11901644

    申请日：2007-09-18

    Applicant: Wei Liu ,  Lixin Su ,  Youfeng Wu ,  Herbert Hum

    Inventor： Wei Liu ,  Lixin Su ,  Youfeng Wu ,  Herbert Hum

    IPC: G06F9/44 ,  G06F9/38

    CPC classification number: G06F8/433

    Abstract: In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG into a topological order, form strands from the nodes based on hardware constraints, rule constraints, and scheduling constraints, and generate executable code for the strands and store the executable code in a storage. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种形成指令串的软件控制方法。 软件可以包括用于获得包括多个基本块的超级块的代码的指令，为代码构建依赖性有向非循环图（DAG），将依赖性DAG的边缘耦合的分类节点排列成拓扑顺序，从节点形成线 基于硬件约束，规则约束和调度约束，并且生成链的可执行代码并将可执行代码存储在存储器中。 描述和要求保护其他实施例。

    Protecting tag information in a multi-level cache hierarchy
    36.
    发明申请
    Protecting tag information in a multi-level cache hierarchy 审中-公开
    保护多级缓存层次结构中的标签信息

    公开(公告)号：US20090019306A1

    公开(公告)日：2009-01-15

    申请号：US11827197

    申请日：2007-07-11

    Applicant: Herbert Hum ,  Rajagopal K. Narayanan

    Inventor： Herbert Hum ,  Rajagopal K. Narayanan

    IPC: G06F11/00

    CPC classification number: G06F12/0811 ,  G06F11/1064 ,  G06F2212/1032 ,  Y02D10/13

    Abstract: In one embodiment, the present invention includes a shared cache memory that is inclusive with other cache memories coupled to it. The shared cache memory includes error correction logic to correct an error present in a tag array of one of the other cache memories and to provide corrected tag information to replace a tag entry in the tag array including the error. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括与其耦合的其它高速缓冲存储器包含的共享高速缓存存储器。 共享高速缓冲存储器包括纠错逻辑，用于校正存在于其它高速缓存存储器之一的标签阵列中的错误，并提供校正标签信息以替换包括错误的标签阵列中的标签条目。 描述和要求保护其他实施例。

    Compressing and accessing a microcode ROM
    37.
    发明申请
    Compressing and accessing a microcode ROM 有权
    压缩和访问微码ROM

    公开(公告)号：US20070022279A1

    公开(公告)日：2007-01-25

    申请号：US11186240

    申请日：2005-07-20

    Applicant: Youfeng Wu ,  Sangwook Kim ,  Mauricio Breternitz ,  Herbert Hum

    Inventor： Youfeng Wu ,  Sangwook Kim ,  Mauricio Breternitz ,  Herbert Hum

    IPC: G06F9/44

    CPC classification number: G06F12/06 ,  G06F8/4436 ,  G06F9/30178 ,  G06F2212/401

    Abstract: An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into different clusters and identifies unique patterns within each cluster. Only unique patterns identified in each cluster are stored in a pattern storage. Indices, which help map an address of a microcode word (“uOP”) to be fetched from a uROM to unique patterns required for the uOP, may be stored in an index storage. Typically it takes a longer time to fetch a uOP from a compressed uROM than from an uncompressed uROM. The compressed uROM may be so designed that the process of fetching a uOP (or uOPs) from a compressed uROM may be fully-pipelined to reduce the access latency.

    Abstract translation: 提供了一种用于在处理器中压缩微代码ROM（“uROM”）并有效访问压缩的“uROM”的装置。 可以使用基于聚类的方法来有效地压缩uROM。 该方法将相似的微代码列组合成不同的集群，并识别每个集群内的唯一模式。 每个集群中唯一标识的模式都存储在模式存储中。 帮助将从uROM获取的微代码字（“uOP”）的地址映射到uOP所需的唯一模式的索引可以存储在索引存储器中。 通常，从压缩的uROM获取uop比从未压缩的uROM获取更长的时间。 压缩的uROM可以被设计成使得从压缩的uROM获取uop（或uop）的过程可以被完全流水线化以减少访问等待时间。

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