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公开(公告)号：US09048103B2
公开(公告)日：2015-06-02
申请号：US11988305
申请日：2006-06-26
申请人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
发明人： Yoshio Shimoida , Hideaki Tanaka , Tetsuya Hayashi , Masakatsu Hoshi , Shigeharu Yamagami , Noriaki Kawamoto , Takayuki Kitou , Mineo Miura , Takashi Nakamura
IPC分类号： H01L21/336 , H01L21/3105 , H01L29/78 , H01L21/04 , H01L29/267 , H01L29/66 , H01L29/16 , H01L29/772
CPC分类号： H01L21/049 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).
摘要翻译： 公开了一种用于制造半导体器件（20）的方法。 半导体器件（20）包括：1）半导体衬底（1,2），2）异质半导体区域（3），被配置为接触半导体衬底（1,2）的第一主面（1A） 所述半导体衬底（1,2）具有带隙，3）栅极电极（7）经由栅极绝缘膜（6）与所述异质半导体区域（3）之间的接合部分（13）的一部分 半导体衬底（1,2），4）构造成连接到所述异质半导体区域（3）的源电极（8），以及5）被配置为与所述半导体衬底（1,2）形成欧姆连接的漏电极（9） 2）。 该方法包括以下顺序操作：i）形成栅绝缘膜（6）; 和ii）氮化所述栅极绝缘膜（6）。
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公开(公告)号：US07768035B2
公开(公告)日：2010-08-03
申请号：US12066145
申请日：2006-08-02
IPC分类号： H01L31/0328
CPC分类号： H01L29/0847 , H01L21/0445 , H01L29/0696 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device has a semiconductor base of a first conductivity type; a hetero semiconductor region in contact with the semiconductor base; a gate electrode adjacent to a portion of a junction between the hetero semiconductor region and the semiconductor base across a gate insulating film; a source electrode connected to the hetero semiconductor region; and a drain electrode connected to the semiconductor base. The hetero semiconductor region has a band gap different from that of the semiconductor base. The hetero semiconductor region includes a first hetero semiconductor region and a second hetero semiconductor region. The first hetero semiconductor region is formed before the gate insulating film is formed. The second hetero semiconductor region is formed after the gate insulating film is formed.
摘要翻译： 半导体器件具有第一导电类型的半导体基底; 与半导体基底接触的异质半导体区域; 与栅极绝缘膜相邻的异质半导体区域和半导体基底之间的结的部分相邻的栅电极; 连接到所述异质半导体区的源电极; 以及连接到半导体基底的漏电极。 异质半导体区域具有与半导体基底不同的带隙。 异质半导体区域包括第一异质半导体区域和第二异质半导体区域。 在形成栅极绝缘膜之前形成第一异质半导体区域。 在形成栅极绝缘膜之后形成第二异质半导体区域。
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公开(公告)号：US07749845B2
公开(公告)日：2010-07-06
申请号：US11988944
申请日：2006-06-26
IPC分类号： H01L21/336
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： A method of manufacturing a semiconductor device having a polycrystalline silicon layer (5) includes; a step of forming a mask layer (7) on the polycrystalline silicon layer (5); a step of forming a side wall (8) that is provided on a side face of the mask layer (7) and covers part of the polycrystalline silicon layer (6); a step of doping an impurity (52) into the polycrystalline silicon layer (5) by using at least one of the mask layer (7) and the side wall (8) as a mask; and a step of etching the polycrystalline silicon layer (5, 6) by using at least one of the mask layer (7) and the side wall (8) as a mask.
摘要翻译： 一种制造具有多晶硅层（5）的半导体器件的方法包括： 在多晶硅层（5）上形成掩模层（7）的步骤; 形成设置在掩模层（7）的侧面并覆盖多晶硅层（6）的一部分的侧壁（8）的步骤; 通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模将杂质（52）掺杂到多晶硅层（5）中的步骤; 以及通过使用掩模层（7）和侧壁（8）中的至少一个作为掩模来蚀刻多晶硅层（5,6）的步骤。
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公开(公告)号：US20090200575A1
公开(公告)日：2009-08-13
申请号：US12423207
申请日：2009-04-14
IPC分类号： H01L29/78
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： A semiconductor device is provided with a semiconductor region, a gate electrode, a source electrode and a drain electrode. The semiconductor region is formed on a semiconductor substrate surface and includes a first semiconductor portion of a first conducting type, a second semiconductor portion of a second conducting type, a band gap distinct from the substrate's band gap, more than two accumulated semiconductor layers, and junctions between the layers. The semiconductor layers each contain an impurity of the first conducting type. The gate electrode adjoins a heterojunction between the second semiconductor portion and the semiconductor substrate through a gate insulation film. The source electrode is coupled to the semiconductor region. The drain electrode is coupled to the semiconductor substrate.
摘要翻译： 半导体器件设置有半导体区域，栅极电极，源极电极和漏极电极。 半导体区域形成在半导体衬底表面上，并且包括第一导电类型的第一半导体部分，第二导电类型的第二半导体部分，与衬底带隙不同的带隙，多于两个的累积半导体层，以及 层之间的交叉点。 半导体层各自含有第一导电类型的杂质。 栅极通过栅极绝缘膜与第二半导体部分和半导体衬底之间的异质结相邻。 源电极耦合到半导体区域。 漏电极耦合到半导体衬底。
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公开(公告)号：US07436004B2
公开(公告)日：2008-10-14
申请号：US11289460
申请日：2005-11-30
申请人： Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Tetsuya Hayashi , Toshiro Shinohara , Shigeharu Yamagami
发明人： Yoshio Shimoida , Masakatsu Hoshi , Hideaki Tanaka , Tetsuya Hayashi , Toshiro Shinohara , Shigeharu Yamagami
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L31/111
CPC分类号： H01L29/7398 , H01L29/0834 , H01L29/1608 , H01L29/267 , H01L29/7391 , H01L29/7392 , H01L29/7395 , H01L29/7397
摘要： An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.
摘要翻译： 本发明的一个方面提供一种半导体器件，其包括：第一导电类型的第一半导体本体，设置在第一半导体本体上的第一开关机构，被配置和布置成用于接通流过半导体器件的导通/截止电流;以及 设置在所述半导体本体上的第一反向阻挡异质结二极管，被配置和布置成阻止与所述第一开关机构相反的电流接通/断开。
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公开(公告)号：US20080121933A1
公开(公告)日：2008-05-29
申请号：US11870561
申请日：2007-10-11
IPC分类号： H01L29/778 , H01L21/04 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7828
摘要： Methods of manufacturing a semiconductor device and resulting products. The semiconductor device includes a semiconductor substrate, a hetero semiconductor region hetero-adjoined with the semiconductor substrate, a gate insulation layer contacting the semiconductor substrate and a heterojunction of the hetero semiconductor region, a gate electrode formed on the gate insulation layer, an electric field alleviation region spaced apart from a heterojunction driving end of the heterojunction that contacts the gate insulation layer by a predetermined distance and contacting the semiconductor substrate and the gate insulation layer, a source electrode contacting the hetero semiconductor region and a drain electrode contacting the semiconductor substrate. A mask layer is formed on the hetero semiconductor region, and the electric field alleviation region and the heterojunction driving end are formed by using at least a portion of the first mask layer.
摘要翻译： 制造半导体器件和所得产品的方法。 半导体器件包括半导体衬底，与半导体衬底异质连接的异质半导体区域，与半导体衬底接触的栅极绝缘层和异质半导体区域的异质结，形成在栅极绝缘层上的栅电极，电场 与异质结的异质结驱动端隔开预定距离并接触半导体衬底和栅极绝缘层，与异质半导体区接触的源极和与半导体衬底接触的漏电极的缓冲区。 在异质半导体区域上形成掩模层，并且通过使用第一掩模层的至少一部分形成电场缓和区域和异质结驱动端。
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公开(公告)号：US20060223274A1
公开(公告)日：2006-10-05
申请号：US11377909
申请日：2006-03-16
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/78 , H01L21/047 , H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/772 , H01L29/7828
摘要： In general, this disclosure describes a semiconductor device that exhibits an increased resistance and reduced leakage current in a reverse-biased state, and a method for manufacturing such a semiconductor device. For example, in one embodiment, the increased resistance in the reverse-biased state is obtained by introducing either a P+ or P− type impurity in a polycrystalline silicon layer formed on an N− type epitaxial layer. Additionally, the semiconductor device maintains a low resistance in a forward-biased state. To keep the forward-biased resistance low, the polycrystalline silicon layer in the vicinity of a gate electrode may be of an N+ type. Furthermore, an N+ type source extracting region is formed on the surface of the polycrystalline silicon layer to connect a source electrode to a drain electrode and maintain a low resistance when forward-biased.
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38.发明授权公开(公告)号：US08067776B2
公开(公告)日：2011-11-29
申请号：US12105318
申请日：2008-04-18
IPC分类号： H01L29/12 , H01L29/76 , H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L29/66068 , H01L29/513 , H01L29/7828
摘要： Methods of manufacturing a semiconductor device including a semiconductor substrate and a hetero semiconductor region including a semiconductor material having a band gap different from that of the semiconductor substrate and contacting a portion of a first surface of the semiconductor substrate are taught herein, as are the resulting devices. The method comprises depositing a first insulating film on exposed portions of the first surface of the semiconductor substrate and on exposed surfaces of the hetero semiconductor material and forming a second insulating film between the first insulating film and facing surfaces of the semiconductor substrate and the hetero semiconductor region by performing a thermal treatment in an oxidizing atmosphere.
摘要翻译： 本文教导了制造包括半导体衬底和包括具有与半导体衬底的带隙不同的带隙并与半导体衬底的第一表面的一部分接触的半导体材料的半导体区域的半导体器件的制造方法， 设备。 该方法包括在半导体衬底的第一表面的暴露部分和异质半导体材料的暴露表面上沉积第一绝缘膜，并在第一绝缘膜和半导体衬底和异质半导体的相对表面之间形成第二绝缘膜 通过在氧化气氛中进行热处理。
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公开(公告)号：US07989295B2
公开(公告)日：2011-08-02
申请号：US13014190
申请日：2011-01-26
IPC分类号： H01L21/336
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/1608 , H01L29/267 , H01L29/66068
摘要： A semiconductor substrate made of a semiconductor material is prepared, and a hetero semiconductor region is formed on the semiconductor substrate to form a heterojunction in an interface between the hetero semiconductor region and the semiconductor substrate. The hetero semiconductor region is made of a semiconductor material having a bandgap different from that of the semiconductor material, and a part of the hetero semiconductor region includes a film thickness control portion whose film thickness is thinner than that of the other part thereof. By oxidizing the hetero semiconductor region with a thickness equal to the film thickness of the film thickness control portion, a gate insulating film adjacent to the heterojunction is formed. A gate electrode is formed on the gate insulating film. This makes it possible to manufacture a semiconductor device including the gate insulating film with a lower ON resistance, and with a higher insulating characteristic and reliability.
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公开(公告)号：US07902555B2
公开(公告)日：2011-03-08
申请号：US12325377
申请日：2008-12-01
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/0847 , H01L29/0623 , H01L29/0642 , H01L29/0646 , H01L29/0649 , H01L29/0696 , H01L29/1608 , H01L29/267 , H01L29/7828
摘要： A hetero semiconductor corner region, which is a current-concentration relief region that keeps a reverse bias current from concentrating on the convex corner, is arranged in a hetero semiconductor region. Thereby, a current concentration on the convex corner can be prevented. As a result, an interrupting performance can be improved at the time of interruption, and at the same time, the generation of the hot spot where in a specific portion is prevented at the time of conduction to suppress deterioration in a specific portion, thereby ensuring a long-term reliability. Further, when the semiconductor chip is used in an L load circuit or the like, for example, at the time of conduction or during a transient response time to the interrupted state, in an index such as a short resistant load amount and an avalanche resistant amount, which are indexes of a breakdown tolerance when overcurrent or overvoltage occurs, the current concentration on a specific portion can be prevented, and thus, these breakdown tolerances can also be improved.
摘要翻译： 作为将反向偏置电流保持集中在凸角上的电流 - 浓度释放区域的异质半导体角区域设置在异质半导体区域中。 由此，可以防止凸角上的电流集中。 结果，在中断时可以提高中断性能，同时，在导通时防止特定部位的热点的产生，抑制特定部分的劣化，从而确保 长期可靠。 此外，例如在导通时或半导体芯片用于L负载电路等时，例如，在短时间响应时间到中断状态时，以诸如短路负载量和雪崩阻抗的指标 量是当发生过电流或过电压时的击穿容限的指标，可以防止特定部分上的电流浓度，因此也可以提高这些击穿公差。
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