公开(公告)号：US5559750A

公开(公告)日：1996-09-24

申请号：US465472

申请日：1995-06-05

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5270977A

公开(公告)日：1993-12-14

申请号：US751934

申请日：1991-09-03

申请人： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

发明人： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

IPC分类号： G01R31/28 ,  G11C7/00 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/4072 ,  G11C11/46 ,  G11C29/46

摘要： Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.

摘要翻译： 公开了一种包括能够在短时间内测试多个存储单元是否有故障的测试模式操作的DRAM。 DRAM包括上电检测信号发生器，上电复位信号发生器和测试模式指令信号发生器。 上电检测信号发生器检测电源电压的应用并产生上电检测信号。 上电复位信号发生器由上电复位信号复位，至少在复位后施加一次外部和上升沿和R信号并产生上电复位信号。 测试模式指令信号发生器检测内部RAS信号，内部CAS信号和上电复位后施加的内部W信号的逻辑状态，并产生测试模式指令信号。

公开(公告)号：US5010259A

公开(公告)日：1991-04-23

申请号：US454580

申请日：1989-12-21

申请人： Yoshinori Inoue ,  Masaki Kumanoya ,  Takahiro Komatsu ,  Yasuhiro Konishi ,  Katsumi Dosaka

发明人： Yoshinori Inoue ,  Masaki Kumanoya ,  Takahiro Komatsu ,  Yasuhiro Konishi ,  Katsumi Dosaka

IPC分类号： G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H02M3/07 ,  H03K5/02 ,  H03K19/017 ,  H03K19/094

CPC分类号： H03K19/01714

摘要： An input signal is inverted by a CMOS inverter and provided for an output signal line. The CMOS inverter is provided between a power supply and a ground, and its node on the side of the power supply is charged all the time to prevent the potential thereof from being lowered. An output signal provided for the output signal line is delayed by a delay circuit to be applied to a boosting capacitor. The potential of the node is further boosted by this boosting capacitor. Consequently, the potential of the output signal is also boosted. When the potential of the node is raised higher than a supply voltage, an N channel MOSFET for charging is turned off to prevent a reverse flow of a charge.

摘要翻译： 输入信号由CMOS反相器反相并提供给输出信号线。 CMOS反相器设置在电源和地之间，并且其电源侧的节点一直被充电以防止其电位降低。 为输出信号线提供的输出信号被延迟电路延迟以施加到升压电容器。 该升压电容器进一步提升了节点的电位。 因此，输出信号的电位也得到提升。 当节点的电位升高到高于电​​源电压时，用于充电的N沟道MOSFET关闭，以防止电荷反向流动。

公开(公告)号：USRE36875E

公开(公告)日：2000-09-19

申请号：US572516

申请日：1995-12-14

申请人： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

发明人： Hisashi Iwamoto ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Akira Yamazaki

IPC分类号： G01R31/28 ,  G11C7/00 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  H01L21/66 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/4072 ,  G11C11/46 ,  G11C29/46

摘要： Disclosed is a DRAM including a test mode operation capable of testing whether a plurality of memory cells are defective or not in a short time. The DRAM includes a power-on detection signal generator, a power-on reset signal generator, and a test mode instruction signal generator. The power-on detection signal generator detects application of a power supply voltage and generates a power-on detection signal. The power-on reset signal generator is reset by a power-on reset signal, counts at least once an external RAS signal applied after reset and generates a power-on reset signal. The test mode instruction signal generator detects logic states of an internal RAS signal, an internal CAS signal and an internal W signal applied after the power-on reset and generates a test mode instructing signal.

摘要翻译： 公开了一种包括能够在短时间内测试多个存储单元是否有故障的测试模式操作的DRAM。 DRAM包括上电检测信号发生器，上电复位信号发生器和测试模式指令信号发生器。 上电检测信号发生器检测电源电压的应用并产生上电检测信号。 上电复位信号发生器由上电复位信号复位，至少一次外部+ E计数，复位后施加RAS + EE信号，并产生上电复位信号。 测试模式指令信号发生器检测内部RAS信号，内部CAS信号和上电复位后施加的内部W信号的逻辑状态，并产生测试模式指令信号。

公开(公告)号：US5629895A

公开(公告)日：1997-05-13

申请号：US639997

申请日：1996-04-30

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5583813A

公开(公告)日：1996-12-10

申请号：US461916

申请日：1995-06-05

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5544121A

公开(公告)日：1996-08-06

申请号：US463565

申请日：1995-06-05

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC分类号： G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC分类号： G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US4984210A

公开(公告)日：1991-01-08

申请号：US565400

申请日：1990-08-10

申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Youichi Tobita

发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Youichi Tobita

IPC分类号： G11C11/407 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4076

CPC分类号： G11C11/406 ,  G11C11/4076

摘要： In a dynamic random access memory (DRAM), there is provided a refresh decision circuit which detects the external designation of a self refresh mode, in addition to a CAS before RAS refresh mode, by RAS and CAS signals. By detecting a time period of one cycle of the RAS, the self refresh mode is determined. As a result, the timing of change of the RAS signal is less restricted.

公开(公告)号：US4954992A

公开(公告)日：1990-09-04

申请号：US269757

申请日：1988-11-08

申请人： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

发明人： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC分类号： G11C7/1057 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/062 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

摘要： A dynamic random access memory device includes a pair of write-in data transferring buses for transferring data to be written, a pair of read-out data transferring buses for transferring data to be read provided additionally and separately from the write-in data transferring bus pair and a plurality of current mirror type sense amplifiers formed of CMOS transistors and each amplifier being provided between a bit line pair and the read-out data transferring bus pair and having input nodes connected to the corresponding bit line pair and the read-out data transferring bus pair forming output nodes thereof. The current mirror type sense amplifiers of CMOS transistors are activated in response to an output of a column decoder at earlier time than the time when conventional flip-flop type sense amplifiers are activated.

摘要翻译： 一种动态随机存取存储器件包括一对写入数据传送总线，用于传送要被写入的数据，一对读出数据传输总线，用于传送要被读取的数据，附加地和独立于写入数据传输总线 对和由CMOS晶体管形成的多个电流镜型读出放大器，并且每个放大器设置在位线对和读出数据传输总线对之间，并且具有连接到相应位线对和读出数据的输入节点 传输总线对形成其输出节点。 响应于比传统的触发器型读出放大器被激活的时间早的列解码器的输出，CMOS晶体管的电流镜式读出放大器被激活。

公开(公告)号：US4943960A

公开(公告)日：1990-07-24

申请号：US337976

申请日：1989-04-14

申请人： Takahiro Komatsu ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi

发明人： Takahiro Komatsu ,  Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C11/406 ,  G11C11/4074

摘要： There is disclosed a dynamic random access memory device of the type capable of periodic self-refresh cycles of operation. The DRAM includes the detector circuit for detecting the designation of the self-refresh mode and a voltage generator circuit for generating a voltage to precharge the bit line pair. During the self-controlled refresh cycle, the bit line pair is equalized and precharged to a voltage lower than Vcc/2. When it is attempted to set the time interval between the self-refresh cycles in order to reduce current consumption, the level of voltage stored in the memory cell capacitor tends to decrease due to charge leakage. However, it is implemented to provide and keep a potential difference between the precharge voltage on the bit line pair and the voltage stored in the capacitor thereby to secure the desired sensing margin for the sense amplifier.

摘要翻译： 公开了一种能够进行周期性自刷新操作周期的动态随机存取存储器件。 DRAM包括用于检测自刷新模式的指定的检测器电路和用于产生用于对位线对预充电的电压的电压发生器电路。 在自控刷新周期期间，位线对被均衡并预充电到低于Vcc / 2的电压。 当为了减少电流消耗而尝试设置自刷新周期之间的时间间隔时，由于电荷泄漏，存储在存储单元电容器中的电压电平趋于降低。 然而，实现了提供并保持位线对上的预充电电压和存储在电容器中的电压之间的电位差，从而确保感测放大器所需的感测余量。