公开(公告)号：US20140312700A1

公开(公告)日：2014-10-23

申请号：US14354012

申请日：2012-10-05

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Maria-Iro Baka

IPC: G05F1/67 ,  H02J1/00

CPC classification number: G05F1/67 ,  H01L31/02021 ,  H02J1/00 ,  Y02E10/50 ,  Y10T307/685

Abstract: A PV module is described with an array of PV cells whereby the module is reconfigurable, allowing different configurations to be applied after installation and during operation, i.e. at run-time. The run time configuration of the module has controllable devices. The main controllable devices are any of (individually or in combination): a) switches which determine the parallel/series connections of the cells as well as hybrid cases also. b) switches between the cells and local dc/dc converters and/or among the DC/DC converters; c) actively controlled bypass diodes placed in order to allow excess current to flow in the occurrence of a mismatch.

Abstract translation: PV模块用PV阵列阵列描述，由此模块是可重新配置的，允许在安装和运行之后（即运行时）应用不同的配置。 该模块的运行时间配置具有可控制的设备。 主要的可控制装置是（单独或组合）中的任何一种：a）确定电池的并联/串联连接以及混合电池的开关。 b）在单元和本地dc / dc转换器之间切换和/或在DC / DC转换器之间切换; c）主动控制的旁路二极管放置，以便在发生不匹配时允许过电流流动。

公开(公告)号：US12164849B2

公开(公告)日：2024-12-10

申请号：US17039571

申请日：2020-09-30

Applicant: IMEC vzw

Inventor： Subrat Mishra ,  Pieter Weckx ,  Francky Catthoor ,  Alessio Spessot

IPC: G06F30/3308 ,  G06F30/367 ,  G06F30/392 ,  G06F30/398 ,  G06F115/06 ,  G06F119/04

Abstract: A system and method of simulating device aging based on a digital waveform representative of a workload of an electronic device are disclosed. In one aspect, the method comprises grouping contiguous sets of cycles into segments, each set corresponding to a segment. Each segment has values for a combination of segment parameters that are unique from each of the other segments and a start point that is separated from a start point of an adjacent segment by a pre-defined distance criterion. Grouping the sets into the segments comprises, for each segment: sampling one or more sequential cycles of the workload, generating the segment based on the sampled contiguous cycles having a period exceeding a threshold period, and determining the values for the combination of segment parameters. The method further comprises applying an aging model to the segments to simulate the aging. The segments are a representation of the digital waveform.

公开(公告)号：US10732350B2

公开(公告)日：2020-08-04

申请号：US16100016

申请日：2018-08-09

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Odysseas Zografos ,  Francky Catthoor ,  Sourav Dutta ,  Azad Naeemi

IPC: G02B6/10 ,  G02B6/122 ,  G01N21/552 ,  G02B5/00 ,  G02B6/125 ,  B82Y20/00

Abstract: A plasmonic device comprising an odd number of at least three input waveguides and at least one output waveguide is disclosed. In one aspect, the waveguides are adapted for guiding a surface plasmon polariton wave and the input waveguides are connected to the output waveguide at a waveguide junction. The inserted SPP waves have a phase at the waveguide junction which is either a first phase or a second phase. The second phase is shifted over π with regard to the first phase and a combined SPP wave at the waveguide junction has a resulting phase wherein the dimensions of the waveguides are such that for different combinations of phases of the inserted waves the combined waves are phase aligned.

公开(公告)号：US20190034111A1

公开(公告)日：2019-01-31

申请号：US16028328

申请日：2018-07-05

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Daniele Garbin ,  Dimitrios Rodopoulos ,  Odysseas Zografos

IPC: G06F3/06 ,  G06N3/08

CPC classification number: G06F3/0646 ,  G06F3/0604 ,  G06F3/0673 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N3/088 ,  G11C7/1006 ,  G11C11/54 ,  G11C13/0002 ,  G11C13/0061 ,  G11C16/04 ,  G11C17/165 ,  G11C2213/71

Abstract: A control plane for controlling transfer of data to a data plane is disclosed. In one aspect, the control plane comprises memory cells for storing a digitally coded parameter value and having a data input electrode, a data output electrode and a control electrode, n data input terminals that receive a data input value and apply it to the data input electrode of an associated memory cell, and n data output terminals coupled to a data output electrode of an associated memory cell. The control plane further comprise a first delay line having delay elements and arranged for receiving a stream of control bit values, and a second delay line having delay elements and arranged for receiving a signal for enabling the control bit values in the first delay line, wherein data is transferred in a controlled and synchronized fashion to an output electrode.

公开(公告)号：US10192009B2

公开(公告)日：2019-01-29

申请号：US14856100

申请日：2015-09-16

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Hans Goverde ,  Francky Catthoor ,  Vikas Dubey ,  Jef Poortmans ,  Christiaan Baert

IPC: G06F17/50 ,  H02S50/10 ,  G06F17/10 ,  H02S50/00

Abstract: A method is provided for calculating a performance of a photovoltaic module comprising at least a first photovoltaic cell and a second photovoltaic cell. The method comprises calculating a heat flow between the first photovoltaic cell and the second photovoltaic cell using a first thermal equivalent circuit of the first photovoltaic cell and a second thermal equivalent circuit of the second photovoltaic cell, wherein at least one node of the first thermal equivalent circuit is connected to a corresponding node of the second thermal equivalent circuit by a thermal coupling resistance. The method may be used for calculating the influence of spatial and temporal variations in the operation conditions on the performance, such as the energy yield, of a photovoltaic module or a photovoltaic system.

公开(公告)号：US10019361B2

公开(公告)日：2018-07-10

申请号：US15250188

申请日：2016-08-29

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Praveen Raghavan ,  Matthias Hartmann ,  Komalan Manu Perumkunnil ,  Jose Ignacio Gomez ,  Christian Tenllado

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0893 ,  G06F12/0897 ,  G11C7/10 ,  G11C11/16 ,  G06F15/78 ,  G06F13/16

CPC classification number: G06F12/0811 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0685 ,  G06F3/0688 ,  G06F8/41 ,  G06F8/452 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/0897 ,  G06F13/1657 ,  G06F13/1673 ,  G06F15/781 ,  G06F15/7846 ,  G06F2212/1016 ,  G06F2212/222 ,  G06F2212/454 ,  G06F2212/601 ,  G06F2212/6028 ,  G11C7/10 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675

Abstract: The present disclosure relates to low-layer memory for a computing platform. An example embodiment includes a memory hierarchy being directly connectable to a processor. The memory hierarchy includes at least a level 1, referred to as L1, memory structure comprising a non-volatile memory unit as L1 data memory and a buffer structure (L1-VWB). The buffer structure includes a plurality of interconnected wide registers with an asymmetric organization, wider towards the non-volatile memory unit than towards a data path connectable to the processor. The buffer structure and the non-volatile memory unit are arranged for being directly connectable to a processor so that data words can be read directly from either of the L1 data memory and the buffer structure (L1-VWB) by the processor.