公开(公告)号：US11342285B2

公开(公告)日：2022-05-24

申请号：US17002829

申请日：2020-08-26

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H01L23/00 ,  H01L23/528 ,  H01L27/092 ,  H01L27/02

Abstract: A semiconductor chip may have at least one p-channel field effect transistor (FET), at least one n-channel FET, a first and a second power supply terminal, wherein the at least one n-channel FET, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p-channel FET and the at least one p-channel FET, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n-channel FET, a precharge circuit to precharge the circuit to a first state, and a detection circuit configured to output an alarm signal if the circuit enters a second state.

公开(公告)号：US11171647B2

公开(公告)日：2021-11-09

申请号：US15931966

申请日：2020-05-14

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Berndt Gammel ,  Franz Klug

IPC: H03K19/003 ,  H03K19/094

Abstract: According to one embodiment, an integrated electronic circuit has a switching network configured to receive binary control states, one or more secret-carrying gates, wherein each secret-carrying gate represents Boolean secrets and is configured to receive binary input states and to output one or more Boolean secrets according to a state sequence of the binary input states, and one or more flip-flops configured to store binary output states output by the switching network and to supply binary input states to the one or more secret-carrying gates based on the stored binary output states. The switching network generates the binary output states by combining the binary control states and Boolean secrets output by the one or more secret-carrying gates. The integrated electronic circuit outputs Boolean secrets from the one or more secret-carrying gates and/or the binary output states from the switching network to another integrated electronic circuit.

公开(公告)号：US10804216B2

公开(公告)日：2020-10-13

申请号：US16510371

申请日：2019-07-12

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Hans Friedinger

IPC: H01L23/552 ,  H03K3/037 ,  H03K3/356 ,  G06F21/75 ,  H01L23/00 ,  G06F21/87 ,  H01L27/144

Abstract: A chip having a substrate region having a substrate contact, an RS latch having two complementary nodes representing a storage state of the RS latch, a control circuit having a control input and configured to connect one of the complementary nodes to a supply potential depending on a potential at the control input, wherein the control input is connected to the substrate contact, and an output circuit connected to an output of the RS latch and configured to trigger an alarm depending on the storage state of the RS latch.

公开(公告)号：US10483972B2

公开(公告)日：2019-11-19

申请号：US16183827

申请日：2018-11-08

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H03K19/003 ,  H03K17/00 ,  H04L9/32

Abstract: A delay circuit includes an electronic transmission element with a first input and a first output. The first input is coupled to the first output by two first switches wired in parallel. The first switches each have a control input, a second input and a second output. The second input is coupled to the second output by two second switches wired in parallel. The circuit further includes an input circuit to receive an input signal and feed the input signal to one of the transmission element inputs and feed the inverted input signal to the other of the transmission element inputs, and an output circuit. The output circuit is configured such that the output signal only changes in the case of a change in the input signal if the change in the input signal has brought about a change both at the first output and at the second output.

公开(公告)号：US10276222B2

公开(公告)日：2019-04-30

申请号：US14710617

申请日：2015-05-13

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Gerd Dirscherl ,  Gunther Fenzl ,  Joel Hatsch ,  Nikolai Sefzik

IPC: G11C7/12 ,  G11C11/419 ,  G11C7/10 ,  G11C8/06 ,  G11C8/18 ,  G11C11/408 ,  G11C11/415

Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.

公开(公告)号：US09679167B2

公开(公告)日：2017-06-13

申请号：US14080847

申请日：2013-11-15

Applicant: Infineon Technologies AG

Inventor： Jan Otterstedt ,  Thomas Kuenemund

IPC: G06F21/00 ,  G06F21/87

CPC classification number: G06F21/87

Abstract: According to one embodiment, a chip is described comprising a substrate; an energy source configured to provide energy to the substrate; an energy receiver configured to receive energy from the energy source via the substrate and a determiner configured to determine a value of a parameter of the energy transmission between the energy source and the energy receiver, to check whether the value matches a predetermined value of the parameter and to output a signal depending on the result of the check.

公开(公告)号：US09496872B1

公开(公告)日：2016-11-15

申请号：US14844029

申请日：2015-09-03

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: H03K19/00 ,  H03K19/003 ,  H01L21/8234 ,  H01L23/00 ,  H03K19/094

CPC classification number: H03K19/003 ,  H01L23/576 ,  H03K19/094

Abstract: A method for manufacturing a digital circuit is described including forming a plurality of field effect transistor pairs, connecting the field effect transistors of the field effect transistor pairs such that in response to a first transition from a first state of two nodes of the digital circuit and in response to a second transition from a second state of the nodes of the digital circuit the nodes each have an undefined logic state when, for each field effect transistor pair, the threshold voltages of the field effect transistors of the field effect transistor pair are equal and setting the threshold voltages of the field effect transistors of the field effect transistor pairs such that the nodes each have a predetermined defined logic state in response to the first transition and in response to the second transition.

Abstract translation: 描述了一种制造数字电路的方法，包括形成多个场效应晶体管对，连接场效应晶体管对的场效应晶体管，使得响应于来自数字电路的两个节点的第一状态的第一转变和 响应于来自数字电路的节点的第二状态的第二过渡，节点各自具有未定义的逻辑状态，当对于每个场效应晶体管对，场效应晶体管对的场效应晶体管的阈值电压相等时 以及设置场效应晶体管对的场效应晶体管的阈值电压，使得每个节点响应于第一转变和响应于第二转变而具有预定的定义逻辑状态。

公开(公告)号：US09385726B2

公开(公告)日：2016-07-05

申请号：US14254913

申请日：2014-04-17

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Bernhard Lippmann

IPC: H03K19/21 ,  H01L27/02 ,  H01L27/118 ,  H03K19/177 ,  H01L23/00 ,  H01L21/70 ,  H01L27/088 ,  H01L27/092

CPC classification number: H03K19/215 ,  H01L23/576 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K19/17768 ,  H01L2924/00

Abstract: According to one embodiment, a chip is described comprising a plurality of supply lines delimiting a plurality of cell areas and a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.

Abstract translation: 根据一个实施例，描述了芯片，其包括限定多个单元区域的多个供电线和包括第一晶体管和第二晶体管的栅极，其中第一晶体管位于多个单元区域的第一单元区域中 并且所述第二晶体管位于所述多个单元区域的第二单元区域中，使得所述多条电源线的供电线位于所述第一单元区域和所述第二单元区域之间。

公开(公告)号：US20150028917A1

公开(公告)日：2015-01-29

申请号：US14512686

申请日：2014-10-13

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Dennis Tischendorf ,  Uwe Weder

IPC: H03K19/177 ,  H01L27/144 ,  H01L23/552

CPC classification number: H03K19/17768 ,  G06F21/755 ,  H01L21/761 ,  H01L23/544 ,  H01L23/573 ,  H01L27/04 ,  H01L27/1443 ,  H01L2924/0002 ,  H02H1/00 ,  H01L2924/00

Abstract: A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.

Abstract translation: 半导体部件包括半导体衬底，以及具有阱端子和晶体管结构的掺杂阱，其具有形成在半导体衬底中的至少一个电位端子。 晶体管结构具有寄生晶闸管，并且至少部分地布置在掺杂阱中。 电位端子和阱端子通过电阻连接。

公开(公告)号：US08901979B2

公开(公告)日：2014-12-02

申请号：US14089780

申请日：2013-11-26

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund

IPC: G11C11/41 ,  H03K3/037

CPC classification number: G11C11/41 ,  G11C7/1006 ,  G11C7/1009 ,  H03K3/0372

Abstract: In accordance with an embodiment, a description is given of a storage circuit including an input stage configured to provide a value to be stored, a storage stage configured to store the value to be stored, an output stage configured to output a value stored by the storage circuit, and a control circuit, wherein the control circuit is configured to receive a signal from the output stage, which signal indicates the charge state of the output stage, and, if the charge state of the output stage is equal to a predefined precharge state, to output an activation signal to the storage stage, and wherein the storage stage is configured to store the value to be stored, provided by the input stage, in reaction to the activation signal.

Abstract translation: 根据实施例，给出了包括被配置为提供要存储的值的输入级的存储电路，被配置为存储要存储的值的存储级，输出级，其被配置为输出存储的值 存储电路和控制电路，其中所述控制电路被配置为从所述输出级接收信号，所述信号指示所述输出级的充电状态，并且如果所述输出级的充电状态等于预定义的预充电 状态，以将激活信号输出到所述存储级，并且其中所述存储级被配置为存储由所述输入级提供的要存储的值，以响应于所述激活信号。