公开(公告)号：US20200287006A1

公开(公告)日：2020-09-10

申请号：US16645405

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Li Huey TAN ,  Tristan TRONIC ,  Benjamin CHU-KUNG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a gate electrode above a substrate and a channel layer above the gate electrode. A source electrode may be above the channel layer and adjacent to a source area of the channel layer, and a drain electrode may be above the channel layer and adjacent to a drain area of the channel layer. A passivation layer may be above the channel layer and between the source electrode and the drain electrode, and a top dielectric layer may be above the gate electrode, the channel layer, the source electrode, the drain electrode, and the passivation layer. In addition, an air gap may be above the passivation layer and below the top dielectric layer, and between the source electrode and the drain electrode. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098874A1

公开(公告)日：2020-03-26

申请号：US16141301

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Justin WEBER ,  Harold KENNEL ,  Abhishek SHARMA ,  Christopher JEZEWSKI ,  Matthew V. METZ ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Van H. LE ,  Arnab SEN GUPTA

IPC: H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L29/267 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L21/322

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US20190140061A1

公开(公告)日：2019-05-09

申请号：US16094151

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Jack T. KAVALIEROS ,  Willy RACHMADY ,  Matthew V. METZ ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/768

Abstract: An interlayer film is deposited on a device layer on a substrate. A contact layer is deposited on the interlayer film. The interlayer film has a broken bandgap alignment to the device layer to reduce a contact resistance of the contact layer to the device layer.

公开(公告)号：US20190131187A1

公开(公告)日：2019-05-02

申请号：US16094452

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Van H. LE ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Rafael RIOS ,  Gilbert DEWEY

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/768 ,  H01L23/522

Abstract: A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190058053A1

公开(公告)日：2019-02-21

申请号：US15770628

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Seiyon KIM ,  Benjamin CHU-KUNG

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66583 ,  H01L29/0607 ,  H01L29/0696 ,  H01L29/0882 ,  H01L29/267 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7854

Abstract: Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.

公开(公告)号：US20180366587A1

公开(公告)日：2018-12-20

申请号：US15777117

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20180331195A1

公开(公告)日：2018-11-15

申请号：US15773894

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Benjamin CHU-KUNG ,  Van H. LE ,  Gilbert DEWEY ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/47 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/47 ,  H01L21/28255 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/78

Abstract: An apparatus including a substrate; a transistor device on the substrate including a channel and a source and a drain disposed between the channel; a source contact coupled to the source and a drain contact coupled to the drain; and the source and drain each including a composition including a concentration of germanium at an interface with the channel that is greater than a concentration of germanium at a junction with the source contact. A method including defining an area on a substrate for a transistor device; forming a source and a drain each including an interface with the channel; and forming a contact to one of the source and the drain, wherein a composition of each of the source and the drain includes a concentration of germanium at an interface with the channel that is greater than a concentration at a junction with the contact.

公开(公告)号：US20180261669A1

公开(公告)日：2018-09-13

申请号：US15892182

申请日：2018-02-08

Applicant: Intel Corporation

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Harold Hal W. KENNEL ,  Willy RACHMADY ,  Ravi PILLARISETTY ,  Jack T. KAVALIEROS

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L29/10 ,  H01L29/08 ,  H01L29/15

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/283 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66651 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78687 ,  H01L29/78696

Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and mitigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.

公开(公告)号：US20170323946A1

公开(公告)日：2017-11-09

申请号：US15656480

申请日：2017-07-21

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER ,  Seung Hoon SUNG ,  Robert S. Chau

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/78 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/201 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/285 ,  H01L21/283 ,  H01L29/80

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

公开(公告)号：US20170271448A1

公开(公告)日：2017-09-21

申请号：US15598290

申请日：2017-05-17

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.