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    Profiles for collecting telemetry data
    34.
    发明授权
    Profiles for collecting telemetry data 有权

    公开(公告)号：US10433035B2

    公开(公告)日：2019-10-01

    申请号：US15476077

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Ronen Chayat ,  Andrey Chilikin ,  John J. Browne ,  Chris MacNamara ,  Tomasz Kantecki

    IPC: H04Q9/02

    Abstract: An apparatus includes telemetry registers, a memory, and a virtualized telemetry controller. The memory may store a set of telemetry profiles, including a first telemetry profile specifying a collection trigger, a set of telemetry registers, and a telemetry data destination. The virtualized telemetry controller may be to: detect a condition satisfying the collection trigger specified in the first telemetry profile; in response to a detection of the condition, read telemetry values from the set of telemetry registers specified in the first telemetry profile; generate a telemetry container including the telemetry values; and send the telemetry container to the telemetry data destination specified in the first telemetry profile.

    TECHNOLOGIES FOR BUFFERING RECEIVED NETWORK PACKET DATA
    36.
    发明申请
    TECHNOLOGIES FOR BUFFERING RECEIVED NETWORK PACKET DATA 审中-公开

    公开(公告)号：US20190044893A1

    公开(公告)日：2019-02-07

    申请号：US16024774

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Bruce Richardson ,  Chris MacNamara ,  Patrick Fleming ,  Tomasz Kantecki ,  Ciara Loftus ,  John J. Browne ,  Patrick Connor

    IPC: H04L12/861 ,  H04L12/879

    Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.

    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS
    37.
    发明申请
    TECHNOLOGIES FOR PROVIDING EFFICIENT DETECTION OF IDLE POLL LOOPS 审中-公开

    公开(公告)号：US20190041957A1

    公开(公告)日：2019-02-07

    申请号：US15951391

    申请日：2018-04-12

    Applicant: Intel Corporation

    Inventor： David Hunt ,  Niall Power ,  Kevin Devey ,  Changzheng Wei ,  Bruce Richardson ,  Eliezer Tamir ,  Andrew Cunningham ,  Chris MacNamara ,  Nemanja Marjanovic ,  Rory Sexton ,  John Browne

    IPC: G06F1/32

    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

    MEMORY RING-BASED JOB DISTRIBUTION FOR PROCESSOR CORES AND CO-PROCESSORS
    38.
    发明申请
    MEMORY RING-BASED JOB DISTRIBUTION FOR PROCESSOR CORES AND CO-PROCESSORS 审中-公开

    公开(公告)号：US20180285154A1

    公开(公告)日：2018-10-04

    申请号：US15473885

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： John J. Browne ,  Chris MacNamara ,  Tomasz Kantecki ,  Stephen Doyle ,  Sean Harte ,  Niall Power

    IPC: G06F9/48 ,  G06F9/50

    Abstract: An apparatus includes a processor, a co-processor and a memory ring. The memory ring includes a plurality of slots that are associated with a plurality of jobs. The processor is to apply a set of rules and based on the application of the set of rules, selectively access a first slot of the plurality of slots to read first data stored in the first slot representing a first job of the plurality of jobs and process the first job based on the first data. The co-processor is to apply the set of rules and based on the application of the set of rules, access a second slot of the plurality of slots other than the first slot to read second data representing a second job of the plurality of jobs and process the second job based on the second data.

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