公开(公告)号：US20240063132A1

公开(公告)日：2024-02-22

申请号：US17820993

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Gerald S. Pasdast ,  Johanna M. Swan ,  Henning Braunisch ,  Kimin Jun ,  Jiraporn Seangatith ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Sathya Narasimman Tiagaraj

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/5383 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.

公开(公告)号：US20240030172A1

公开(公告)日：2024-01-25

申请号：US18479014

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Peter Z. Onufryk ,  Gerald S. Pasdast ,  Sathya Narasimman Tiagaraj

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/16 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2224/16145 ,  H01L2924/1431 ,  H01L2924/381

Abstract: Methods and apparatus relating to a Universal Chiplet Interconnect Express™ (UCIe™)-Three Dimensional (UCIe-3D™) interconnect which may be utilized as an on-package interconnect are described. In one embodiment, an interconnect communicatively couples a first physical layer module of a first chiplet on a semiconductor package to a second physical layer module of a second chiplet on the semiconductor package. A first Network-on-chip Controller (NoC) logic circuitry controls the first physical layer module. A second NoC logic circuitry controls the second physical layer module. Other embodiments are also claimed and disclosed.

公开(公告)号：US20230197675A1

公开(公告)日：2023-06-22

申请号：US17552845

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Gerald S. Pasdast ,  Yidnekachew Mekonnen ,  Adel A. Elsherbini ,  Peipei Wang ,  Vivek Kumar Rajan ,  Georgios Dogiamis

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/37001

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first integrated circuit (IC) die, the first IC die comprising an input/output (IO) circuit; and a plurality of IC dies, the plurality of IC dies comprising a second IC die, the second IC die comprising a microcontroller circuit to control the IO circuit, wherein the first IC die and the plurality of IC dies are coupled with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.

公开(公告)号：US20230187407A1

公开(公告)日：2023-06-15

申请号：US17548304

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Carleton L. Molnar ,  Adel A. Elsherbini ,  Tanay Karnik ,  Shawna M. Liff ,  Robert J. Munoz ,  Julien Sebot ,  Johanna M. Swan ,  Nevine Nassif ,  Gerald S. Pasdast ,  Krishna Bharath ,  Neelam Chandwani ,  Dmitri E. Nikonov

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L24/08 ,  H01L24/20 ,  H01L2224/2101 ,  H01L2224/08147 ,  H01L2924/37001 ,  H01L2924/1427

Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

公开(公告)号：US20230163098A1

公开(公告)日：2023-05-25

申请号：US17531374

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  William J. Lambert ,  Krishna Bharath ,  Shawna M. Liff ,  Nicolas Butzen ,  Georgios Dogiamis ,  Gerald S. Pasdast ,  Vivek Kumar Rajan ,  Sathya Narasimman Tiagaraj ,  Timothy Francis Schmidt

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L25/18

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

公开(公告)号：US11581282B2

公开(公告)日：2023-02-14

申请号：US16117353

申请日：2018-08-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Gerald S. Pasdast

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H03M9/00 ,  H01L25/065 ,  H01L25/00

Abstract: In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

公开(公告)号：US20220093725A1

公开(公告)日：2022-03-24

申请号：US17025209

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mohammad Enamul Kabir ,  Zhiguo Qian ,  Gerald S. Pasdast ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Aleksandar Aleksov ,  Feras Eid

IPC: H01L49/02 ,  H01L23/49 ,  H01L23/492

Abstract: Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

公开(公告)号：US20210004347A1

公开(公告)日：2021-01-07

申请号：US17029288

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald S. Pasdast ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/40

Abstract: Systems, methods, and apparatuses associated with an approximate majority based data bus inversion technique are disclosed. A method comprises obtaining, at a first device connected by a plurality of lanes to a second device, original data comprising first bits and second bits, where the first bits are to be transmitted in a new clock cycle via first lanes of the plurality of lanes, and the second bits are to be transmitted in the new clock cycle via second lanes of the plurality of lanes. The method further includes determining whether a first criterion associated with the first bits is met, determining whether a second criterion associated with the second bits is met, and transmitting an inverted version of the original data via the plurality of lanes based, at least in part, on determining that the first criterion and the second criterion are met.

公开(公告)号：US20200098724A1

公开(公告)日：2020-03-26

申请号：US16142509

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Shawna M. Liff ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Gerald S. Pasdast

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/36 ,  H01L25/00

Abstract: Embodiments herein may relate to a semiconductor package or a semiconductor package structure. The package or package structure may include an interposer with a memory coupled to one side and a processing unit coupled to the other side. A third chip may be coupled with the interposer adjacent to the processing unit. Other embodiments may be described and/or claimed.

公开(公告)号：US20200075521A1

公开(公告)日：2020-03-05

申请号：US16117353

申请日：2018-08-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Gerald S. Pasdast

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L25/00 ,  H03M9/00

Abstract: In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.