公开(公告)号：US20220122215A1

公开(公告)日：2022-04-21

申请号：US17428216

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  SELVAKUMAR PANNEER ,  SAURABH TANGRI ,  BEN ASHBAUGH ,  SCOTT JANUS ,  ABHISHEK APPU ,  VARGHESE GEORGE ,  RAVISHANKAR IYER ,  NILESH JAIN ,  PATTABHIRAMAN K ,  ALTUG KOKER ,  MIKE MACPHERSON ,  JOSH MASTRONARDE ,  ELMOUSTAPHA OULD-AHMED-VALL ,  JAYAKRISHNA P. S ,  ERIC SAMSON

IPC: G06T1/60 ,  G06F12/06 ,  G06F12/1009 ,  G06T1/20 ,  G06F12/0875 ,  G06F9/38

Abstract: Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

公开(公告)号：US20220066931A1

公开(公告)日：2022-03-03

申请号：US17310540

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： JOYDEEP RAY ,  NIRANJAN COORAY ,  SUBRAMANIAM MAIYURAN ,  ALTUG KOKER ,  PRASOONKUMAR SURTI ,  VARGHESE GEORGE ,  VALENTIN ANDREI ,  ABHISHEK APPU ,  GUADALUPE GARCIA ,  PATTABHIRAMAN K ,  SUNGYE KIM ,  SANJAY KUMAR ,  PRATIK MAROLIA ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VASANTH RANGANATHAN ,  WILLIAM SADLER ,  LAKSHMINARAYANAN STRIRAMASSARMA

IPC: G06F12/0802

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20200310973A1

公开(公告)日：2020-10-01

申请号：US16366266

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ALTUG KOKER ,  VIDHYA KRISHNAN ,  RONALD W. SILVAS ,  JOHN H. FEIT ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY ,  ABHISHEK R. APPU

IPC: G06F12/0837 ,  G06F9/38 ,  H04L9/06 ,  G06F16/907

Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

公开(公告)号：US20200293488A1

公开(公告)日：2020-09-17

申请号：US16354782

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ARAVINDH ANANTARAMAN ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VALENTIN ANDREI ,  SUBRAMANIAM MAIYURAN ,  NICOLAS GALAPPO VON BORRIES ,  VARGHESE GEORGE ,  MIKE MACPHERSON ,  BEN ASHBAUGH ,  MURALI RAMADOSS ,  VIKRANTH VEMULAPALLI ,  WILLIAM SADLER ,  JONATHAN PEARCE ,  SUNGYE KIM

IPC: G06F15/80 ,  G06T15/00 ,  G06F9/30 ,  G06F9/38

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180293965A1

公开(公告)日：2018-10-11

申请号：US15482535

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  JASON TANNER ,  JOYDEEP RAY ,  ALTUG KOKER ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K

IPC: G09G5/395 ,  G06F9/455 ,  G06T1/60 ,  G09G5/36 ,  G06T15/00 ,  H04N19/42 ,  G06T1/20 ,  G06T9/00

CPC classification number: G09G5/395 ,  G06F3/1423 ,  G06F9/452 ,  G06F9/45533 ,  G06T1/20 ,  G06T1/60 ,  G06T9/004 ,  G06T15/005 ,  G09G3/003 ,  G09G5/36 ,  G09G5/363 ,  G09G2340/02 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2370/022 ,  H04N19/42

Abstract: An apparatus and method are described for efficiently rendering an transmitting to a remote display. For example, one embodiment of a remote display apparatus comprises: a display engine to render a sequence of video images; an encoder to compress the sequence of video images to generate a sequence of compressed video images; a network interface controller to transmit the compressed video images over a network link to a remote display; a plurality of buffer pointer registers to store read pointers and write pointers identifying read locations and write locations, respectively, in a frame buffer and a compressed stream buffer; a central processing unit (CPU) to initialize the read pointers and write pointers for processing one or more of the video images; and the display engine to access a first write pointer to write to a specified location in the frame buffer, the encoder to begin reading from the frame buffer based on a first read pointer value, the encoder to write to the compressed stream buffer based on a second write pointer value, and the network interface controller to read from the compressed stream buffer based on a second read pointer value, the first and second write and read pointer values to be updated without intervention from the CPU as the display engine writes to the frame buffer, the encoder reads from the frame buffer and writes to the compressed stream buffer, and the network interface controller reads from the compressed stream buffer.