公开(公告)号：US20230161615A1

公开(公告)日：2023-05-25

申请号：US18153177

申请日：2023-01-11

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  PHILIP R. LANTZ ,  KUN TIAN ,  UTKARSH Y. KAKAIYA ,  RAJESH M. SANKARAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

公开(公告)号：US20160179687A1

公开(公告)日：2016-06-23

申请号：US14579934

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  RAJESH SANKARAN ,  SUBRAMANYA DULLOOR ,  SHENG LI

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/128 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F3/0671 ,  G06F11/00 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/6028 ,  G06F2212/621

Abstract: A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.

Abstract translation: 处理器包括处理核心，用于执行包括通过包括与事务相关联的高速缓存行的易失性高速缓冲存储器与持久存储器进行交易的指令的应用，所述高速缓存行与高速缓存行状态相关联，高速缓存控制器可操作地耦合 响应于确定高速缓存行被提交的高速缓存行状态，缓存控制器响应于检测到故障事件，将高速缓存行的内容驱逐到永久存储器，并且响应于缓存行 确定指示高速缓存行未被提交的高速缓存行状态，丢弃高速缓存行的内容。

公开(公告)号：US20240345865A1

公开(公告)日：2024-10-17

申请号：US18643932

申请日：2024-04-23

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  PHILIP R. LANTZ ,  KUN TIAN ,  UTKARSH Y. KAKAIYA ,  RAJESH M. SANKARAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

公开(公告)号：US20220066931A1

公开(公告)日：2022-03-03

申请号：US17310540

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： JOYDEEP RAY ,  NIRANJAN COORAY ,  SUBRAMANIAM MAIYURAN ,  ALTUG KOKER ,  PRASOONKUMAR SURTI ,  VARGHESE GEORGE ,  VALENTIN ANDREI ,  ABHISHEK APPU ,  GUADALUPE GARCIA ,  PATTABHIRAMAN K ,  SUNGYE KIM ,  SANJAY KUMAR ,  PRATIK MAROLIA ,  ELMOUSTAPHA OULD-AHMED-VALL ,  VASANTH RANGANATHAN ,  WILLIAM SADLER ,  LAKSHMINARAYANAN STRIRAMASSARMA

IPC: G06F12/0802

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20160364340A1

公开(公告)日：2016-12-15

申请号：US15246811

申请日：2016-08-25

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  RAJESH SANKARAN ,  SUBRAMANYA DULLOOR ,  SHENG LI

IPC: G06F12/128 ,  G06F3/06 ,  G06F12/0808

CPC classification number: G06F12/128 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0653 ,  G06F3/067 ,  G06F3/0671 ,  G06F11/00 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0862 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1027 ,  G06F2212/1032 ,  G06F2212/6028 ,  G06F2212/621

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a near memory cache, wherein the near memory cache comprises a cache line comprising an identifier associated with the transaction and a status flag indicating whether the cache line is committed or uncommitted, and a cache controller operatively coupled to the near memory cache to determine, based on the status flag, what operation is to be performed with respect to contents of the cache line.

Abstract translation: 处理器包括处理核心，用于执行包括经由近程存储器高速缓冲存储器与持久存储器编码事务的指令的应用，其中所述近似存储器高速缓存包括包含与所述事务相关联的标识符的高速缓存行和指示所述高速缓存行 被提交或未提交，以及可操作地耦合到近存储器高速缓存的高速缓存控制器，以基于状态标志来确定要针对高速缓存行的内容执行什么操作。

公开(公告)号：US20160239431A1

公开(公告)日：2016-08-18

申请号：US14621654

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： SHENG LI ,  SANJAY KUMAR ,  VICTOR W. LEE ,  RAJESH M. SANKARAN ,  SUBRAMANYA R. DULLOOR

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1045 ,  G06F9/467 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/69

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.

Abstract translation: 处理器包括处理核心，用于执行包括经由非永久性高速缓冲存储器与永久存储器编码事务的指令的应用程序，其中事务是创建从虚拟地址空间到由存储器区域标识符（ MRID），并且使用其中高速缓存行与高速缓存行状态相关联的MRID和高速缓存控制器将非持续高速缓存的高速缓存行标记为响应于检测到故障事件而选择性地 基于高速缓存行状态将高速缓存行的内容推送到由MRID标识的存储器区域。