公开(公告)号：US20210328019A1

公开(公告)日：2021-10-21

申请号：US17364985

申请日：2021-07-01

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

公开(公告)号：US11114530B2

公开(公告)日：2021-09-07

申请号：US16648442

申请日：2017-12-17

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.

公开(公告)号：US11075293B2

公开(公告)日：2021-07-27

申请号：US16328670

申请日：2016-09-24

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  James S. Clarke

IPC: H01L29/66 ,  H01L29/76 ,  H01L29/775 ,  H01L29/423 ,  H01L29/12 ,  H01L29/06 ,  H01L25/00 ,  H01L25/16 ,  B82Y10/00 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00 ,  H01L25/11 ,  H01L21/56 ,  H01L29/165

Abstract: Disclosed herein are qubit-detector die assemblies, as well as related computing devices and methods. In some embodiments, a die assembly may include: a first die having a first face and an opposing second face, wherein a plurality of active qubit devices are disposed at the first face of the first die; and a second die, mechanically coupled to the first die, having a first face and an opposing second face, wherein a plurality of quantum state detector devices are disposed at the first face of the second die; wherein the first faces of the first and second dies face each other.

公开(公告)号：US10803396B2

公开(公告)日：2020-10-13

申请号：US16011812

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Zachary R. Yoscovits ,  Roman Caudillo ,  Ravi Pillarisetty ,  Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: G06N10/00 ,  H01L27/18 ,  H03K19/195 ,  B82Y10/00 ,  H03K17/92 ,  G11C11/44 ,  H01L45/00 ,  H01L39/22 ,  H01L39/24 ,  H01L29/66

Abstract: Disclosed herein are superconducting qubit devices with Josephson Junctions utilizing resistive switching materials, i.e., resistive Josephson Junctions (RJJs), as well as related methods and quantum circuit assemblies. In some embodiments, an RJJ may include a bottom electrode, a top electrode, and a resistive switching layer (RSL) disposed between the bottom electrode and the top electrode. Using the RSLs in Josephson Junctions of superconducting qubits may allow fine tuning of junction resistance, which is particularly advantageous for optimizing performance of superconducting qubit devices. In addition, RJJs may be fabricated using methods that could be efficiently used in large-scale manufacturing, providing a substantial improvement with respect to approaches for forming conventional Josephson Junctions, such as e.g. double-angle shadow evaporation approach.

公开(公告)号：US20200295164A1

公开(公告)日：2020-09-17

申请号：US16649772

申请日：2018-01-08

Applicant: Intel Corporation

Inventor： Kanwaljit Singh ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Payam Amin ,  Roman Caudillo ,  Hubert C. George ,  Jeanette M. Roberts ,  Zachary R. Yoscovits ,  James S. Clarke ,  Lester Lampert ,  David J. Michalak

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/78 ,  H01L29/778 ,  H01L29/43 ,  H01L29/49 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a first gate above the quantum well stack, wherein the first gate includes a first gate metal; and a second gate above the quantum well stack, wherein the second gate includes a second gate metal, and a material structure of the second gate metal is different from a material structure of the first gate metal; wherein the quantum well layer has a first strain under the first gate, a second strain under the second gate, and the first strain is different from the second strain.

公开(公告)号：US10686007B2

公开(公告)日：2020-06-16

申请号：US16012815

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Adel A. Elsherbini ,  Lester Lampert ,  James S. Clarke ,  Ravi Pillarisetty ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts

IPC: H01L27/18 ,  H01L39/22 ,  H01L49/02 ,  G06N10/00 ,  H01L39/02 ,  H01L39/24 ,  H03K19/195

Abstract: Embodiments of the present disclosure propose quantum circuit assemblies with transmission lines and/or capacitors that include layer-conductors oriented perpendicular to a substrate (i.e. oriented vertically) or a qubit die, with at least portions of the vertical layer-conductors being at least partially buried in the substrate. Such layer-conductors may form ground and signal planes of transmission lines or capacitor plates of capacitors of various quantum circuit assemblies.

公开(公告)号：US10665770B2

公开(公告)日：2020-05-26

申请号：US15913799

申请日：2018-03-06

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Kanwaljit Singh ,  Patrick H. Keys ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  James S. Clarke ,  Roza Kotlyar ,  Payam Amin ,  Jeanette M. Roberts

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/24 ,  H01L39/04 ,  G06N10/00 ,  H01L29/12 ,  H01L27/18 ,  H01L29/66 ,  B82Y10/00 ,  H01L39/14 ,  H01L29/76 ,  H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L21/8234

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a gate above the fin; and a material on side faces of the fin; wherein the fin has a width between its side faces, and the fin is strained in the direction of the width.

公开(公告)号：US10665769B2

公开(公告)日：2020-05-26

申请号：US16011829

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Roman Caudillo ,  Zachary R. Yoscovits ,  Lester Lampert ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L39/02 ,  H01L27/18 ,  H01L39/24 ,  H01L39/04 ,  G06N10/00 ,  H01L39/22

Abstract: Various embodiments of the present disclosure present quantum circuit assemblies implementing vertically-stacked parallel-plate capacitors. Such capacitors include first and second capacitor plates which are parallel to one another and separated from one another by a gap measured along a direction perpendicular to the qubit plane, i.e. measured vertically. Fabrication techniques for manufacturing such capacitors are also disclosed. Vertically-stacked parallel-plate capacitors may help increasing coherence times of qubits, facilitate use of three-dimensional and stacked designs for quantum circuit assemblies, and may be particularly advantageous for realizing device scalability and use of 300-millimeter fabrication processes.

公开(公告)号：US20190392352A1

公开(公告)日：2019-12-26

申请号：US16016840

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Lester Lampert ,  Ravi Pillarisetty ,  Nicole K. Thomas ,  Hubert C. George ,  Jeanette M. Roberts ,  David J. Michalak ,  Roman Caudillo ,  Zachary R. Yoscovits ,  James S. Clarke

IPC: G06N99/00 ,  G06F15/18 ,  G06F17/18 ,  G06F1/20

Abstract: Embodiments of the present disclosure provide quantum circuit assemblies that implement adaptive programming of quantum dot qubit devices. An example quantum circuit assembly includes a quantum circuit component including a quantum dot qubit device, and a control logic coupled to the quantum circuit component. The control logic is configured to adaptively program the quantum dot qubit device by iterating a sequence of applying one or more signals to the quantum dot qubit device, determining a state of at least one qubit of the quantum dot qubit device, and using the determined state to modify the signals to be applied to the quantum dot qubit device in the next iteration. In this manner, the signals may be fine-tuned to achieve a higher probability of the qubit(s) in the quantum dot qubit device being set to the desired state.

公开(公告)号：US20190206993A1

公开(公告)日：2019-07-04

申请号：US16323682

申请日：2016-09-24

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Jeanette M. Roberts ,  Nicole K. Thomas ,  Hubert C. George ,  James S. Clarke

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack with first and second quantum well layers, a first set of gates disposed on the quantum well stack such that the first quantum well layer is disposed between the barrier layer and the first set of gates, a first set of conductive pathways extending from the first set of gates to a first face of the quantum dot device, a second set of gates disposed on the quantum well stack such that the second quantum well layer is disposed between the barrier layer and the second set of gates, and a second set of conductive pathways extending from the second set of gates to a second face of the quantum dot device, wherein the second face is different from the first face.