公开(公告)号：US09502104B2

公开(公告)日：2016-11-22

申请号：US14749337

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： Ravi H. Motwani

IPC: G11C11/34 ,  G11C13/00 ,  G11C16/26 ,  G11C11/56 ,  G06F3/06

CPC classification number: G11C13/004 ,  G06F3/0608 ,  G06F3/0661 ,  G06F3/0679 ,  G11C11/5642 ,  G11C11/5678 ,  G11C16/26

Abstract: Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one embodiment, a receiver may be configured to receive a serial string of values and identify which values in the string are the results of a lower-page read or an upper-page read of the cells. In some embodiments, one signal-level of a three-signal level cell may be represented only by a value in the lower-page read of the cells, while a second signal-level of the three-signal level cell may be represented by a value in the lower-page read of the cells and an upper-page read of the cells.

公开(公告)号：US12113547B2

公开(公告)日：2024-10-08

申请号：US17961410

申请日：2022-10-06

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani

IPC: H03M13/11 ,  H03M13/01 ,  H03M13/15 ,  H03M13/43

CPC classification number: H03M13/1137 ,  H03M13/1157 ,  H03M13/015 ,  H03M13/1125 ,  H03M13/1575 ,  H03M13/43

Abstract: A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

公开(公告)号：US20240134884A1

公开(公告)日：2024-04-25

申请号：US18395311

申请日：2023-12-22

Applicant: Intel Corporation

Inventor： Chendi Xue ,  Jian Zhang ,  Poovaiah Manavattira Palangappa ,  Rita Brugarolas Brufau ,  Ke Ding ,  Ravi H. Motwani ,  Xinyao Wang ,  Yu Zhou ,  Aasavari Dhananjay Kakne

IPC: G06F16/28 ,  G06F16/23

CPC classification number: G06F16/285 ,  G06F16/23

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to preserve privacy in a user dataset including interface circuitry, machine readable instructions, and programmable circuitry to determine a data usage type for each one of a plurality of user data features in a first dataset, classify the data usage type associated with each user data feature of the plurality of user data feature into a feature category, apply at least one feature engineering mechanism to feature categories of the data usage types of the plurality of user data features, select, based on application of feature engineering, a subset of the plurality of user data features for a feature selection training model, and output a second dataset based on the subset of the plurality of user data for the feature selection training model, the second dataset to include fewer user data features than the first dataset.

公开(公告)号：US10547327B2

公开(公告)日：2020-01-28

申请号：US15631476

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Poovaiah Manavattira Palangappa ,  Ravi H. Motwani

IPC: H03M13/11 ,  G05B11/42 ,  G06F11/10

Abstract: Self-configuring error control coding in a memory device provides flexibility in terms of decoding latency, mis-correct probability, and bit-error rate performance, and avoids labor-intensive trial-and-error configuration of decoding algorithm tuning parameters, such as bit flip algorithm thresholds and syndrome-weight maps. A self-configuring decoder for error control coding allows dynamic trading of error floor performance for error rate performance and vice versa based on the performance characteristics of the decoding process.

公开(公告)号：US20200012554A1

公开(公告)日：2020-01-09

申请号：US16578039

申请日：2019-09-20

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Zion S. Kwok

IPC: G06F11/10 ,  G06F7/58 ,  G06F7/76 ,  H03M13/11

Abstract: Embodiments described include methods, apparatuses, and systems including a permutation generator to permute locations of one or more bits (e.g., data bits and/or parity bits) in a codeword. In embodiments, the bits are to be written to a memory device based on the permuted locations to reduce a recurrence of bit error patterns associated with the bits when stored in the memory device. In some embodiments, the locations are based at least in part on a pseudorandom number, generated based at least in part on information available at a read time and a write time. In some embodiments, the pseudorandom number is based upon a memory address of the memory device, such as a 3D NAND or other memory device. Additional embodiments may be described and claimed.

公开(公告)号：US10481974B2

公开(公告)日：2019-11-19

申请号：US15636635

申请日：2017-06-28

Applicant: INTEL CORPORATION

Inventor： Zion S. Kwok ,  Santhosh K. Vanaparthy ,  Ravi H. Motwani

IPC: G06F11/00 ,  G06F11/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.

公开(公告)号：US10454495B2

公开(公告)日：2019-10-22

申请号：US14490307

申请日：2014-09-18

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Pranav Kalavade

IPC: G06F9/38 ,  H03M7/02 ,  H03M5/16 ,  G06F3/00

Abstract: Described is an apparatus for converting binary data to ternary and back such that the apparatus comprises: a first look-up table (LUT) having a mapping of 19 binary bits to 12 ternary trits; and a first logic to receive a binary input and to convert the binary input to a ternary output according to the first LUT.

公开(公告)号：US20190114224A1

公开(公告)日：2019-04-18

申请号：US15787644

申请日：2017-10-18

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Santhosh K. Vanaparthy

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/00 ,  H03M13/11 ,  G11C13/00

Abstract: Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.

公开(公告)号：US10073731B2

公开(公告)日：2018-09-11

申请号：US14091757

申请日：2013-11-27

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Kiran Pangal

IPC: G06F11/10 ,  H03M13/05 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23 ,  H03M13/29

Abstract: Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device for data stored in a memory, retrieve the data and an associated error correction codeword, send the data to a host device, apply an error correction routine to decode the error correction codeword retrieved with the data, and in response to an error in the error correction codeword, send a location of data associated with the error to the host device. Other embodiments are also disclosed and claimed.

公开(公告)号：US10009043B2

公开(公告)日：2018-06-26

申请号：US15197953

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Ravi H. Motwani

IPC: H03M13/00 ,  H03M13/29 ,  H04L29/08 ,  G06F11/10 ,  H03M13/09 ,  H03M13/15

CPC classification number: H03M13/2909 ,  G06F11/1076 ,  H03M13/09 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2933 ,  H03M13/2939 ,  H03M13/2948 ,  H03M13/616 ,  H04L1/00 ,  H04L1/0054 ,  H04L1/0057 ,  H04L69/324

Abstract: Technologies for providing efficient error correction with half product codes include an apparatus having a memory to store data and a controller to manage read and write operations of the memory. The controller is to obtain, in response to a write request, data to write to the memory. The controller is further to encode the data with a half product code to define a matrix that includes at least one matrix element based on a soft decision error correction encoder algorithm and at least one other matrix element based on a hard decision error correction encoder algorithm. Additionally, the controller is to write the half product code to the memory.