公开(公告)号：US11146289B2

公开(公告)日：2021-10-12

申请号：US16370178

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Aman Bhatia ,  Zion S. Kwok ,  Justin Kang ,  Poovaiah M. Palangappa ,  Santhosh K. Vanaparthy

IPC: H03M13/11 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

Abstract: Examples include techniques to use intrinsic information when implementing a bit-flipping algorithm. An error correction control (ECC) decoder uses the intrinsic information to decode a low density parity count (LDPC) codeword. The intrinsic information including bits of a copy of a received LDPC codeword are compared to bits for variable nodes during an iteration of the bit-flipping algorithm to aid a determination as whether one or more bits for the variable nodes are to be flipped.

公开(公告)号：US11777530B2

公开(公告)日：2023-10-03

申请号：US17754152

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Ravi Motwani ,  Poovaiah Palangappa ,  Santosh Emmadi ,  Santhosh K. Vanaparthy ,  Aman Bhatia

IPC: H03M13/35 ,  H03M13/03 ,  H03M13/00 ,  H03M13/11 ,  H03M13/29

CPC classification number: H03M13/353 ,  H03M13/036 ,  H03M13/612 ,  H03M13/1162 ,  H03M13/2948

Abstract: Methods and apparatuses for generating optimized LDPC codes are proposed. One of the methods is a method for generating an optimized LDPC code for an asymmetric transmis¬ sion channel. The method includes receiving an initial LDPC code for the asymmetric transmission channel. Further, the method includes performing a density evolution threshold optimization for the initial LDPC code in order to obtain the optimized LDPC code for the asymmetric transmission channel. A uniformly mixed symmetric channel density for the asymmetric transmission channel is used in the density evolution threshold optimization.

公开(公告)号：US11515891B2

公开(公告)日：2022-11-29

申请号：US17130697

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani

IPC: H03M13/11 ,  H03M13/43 ,  H03M13/01 ,  H03M13/15

Abstract: A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

公开(公告)号：US10579473B2

公开(公告)日：2020-03-03

申请号：US15721291

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani ,  Zion S. Kwok

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/37 ,  G11C29/52 ,  H03M13/15 ,  H03M13/11 ,  G06F11/00

Abstract: One embodiment provides a silent data corruption (SDC) mitigation circuitry. The SDC mitigation circuitry includes a comparator circuitry and an SDC mitigation logic. The comparator circuitry is to compare a successful decoded codeword and a corresponding received codeword, the successful decoded codeword having been deemed a success by an error correction circuitry. The SDC mitigation logic is to reject the successful decoded codeword if a distance between the corresponding received codeword and the successful decoded codeword is greater than or equal to a threshold.

公开(公告)号：US12113547B2

公开(公告)日：2024-10-08

申请号：US17961410

申请日：2022-10-06

Applicant: Intel Corporation

Inventor： Santhosh K. Vanaparthy ,  Ravi H. Motwani

IPC: H03M13/11 ,  H03M13/01 ,  H03M13/15 ,  H03M13/43

CPC classification number: H03M13/1137 ,  H03M13/1157 ,  H03M13/015 ,  H03M13/1125 ,  H03M13/1575 ,  H03M13/43

Abstract: A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.

公开(公告)号：US10481974B2

公开(公告)日：2019-11-19

申请号：US15636635

申请日：2017-06-28

Applicant: INTEL CORPORATION

Inventor： Zion S. Kwok ,  Santhosh K. Vanaparthy ,  Ravi H. Motwani

IPC: G06F11/00 ,  G06F11/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.

公开(公告)号：US20190114224A1

公开(公告)日：2019-04-18

申请号：US15787644

申请日：2017-10-18

Applicant: Intel Corporation

Inventor： Ravi H. Motwani ,  Santhosh K. Vanaparthy

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/00 ,  H03M13/11 ,  G11C13/00

Abstract: Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.

公开(公告)号：US12176918B2

公开(公告)日：2024-12-24

申请号：US17183223

申请日：2021-02-23

Applicant: Intel Corporation

Inventor： Debarnab Mitra ,  Santhosh K. Vanaparthy

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a decoder coupled to the one or more substrates, the decoder including logic to perform a first decode stage with a first fixed quantization width, and perform a second decode stage with a second fixed quantization width that is different from the first fixed quantization width. Other embodiments are disclosed and claimed.

公开(公告)号：US11876622B2

公开(公告)日：2024-01-16

申请号：US17201032

申请日：2021-03-15

Applicant: Intel Corporation

Inventor： Rainer Strobel ,  Santhosh K. Vanaparthy

IPC: H04B10/516 ,  H04B10/69 ,  H04L1/00 ,  H04B10/27 ,  H04B10/50 ,  H04B10/66

CPC classification number: H04L1/0061 ,  H04B10/27 ,  H04B10/50 ,  H04B10/516 ,  H04B10/66 ,  H04B10/69 ,  H04L1/0042 ,  H04L1/0047

Abstract: Examples relate to a Forward Error Correction (FEC) encoder, an FEC decoder, Passive Optical Network (PON) systems, an Optical Line Terminal (OLT), an Optical Networking Unit (ONU), and to corresponding methods and computer programs. A forward-error-correction (FEC) encoder that is suitable for generating FEC data for use with hard-decision input at a receiver and for use with soft-decision input at the receiver is configured to generate the FEC data based on payload bits using a Low-Density Parity-Check (LDPC) code. The generated FEC data is generated using a single LDPC code that is suitable for use with soft-decision input and hard-decision input at the receiver or using one of two LDPC codes that are suitable for soft-decision input and hard-decision input, respectively.

公开(公告)号：US10707901B2

公开(公告)日：2020-07-07

申请号：US16242155

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Poovaiah M Palangappa ,  Ravi H. Motwani ,  Santhosh K. Vanaparthy

IPC: H03M13/11 ,  G06F11/10 ,  G11C29/04 ,  H03M13/37 ,  H03M13/00 ,  H03M13/53

Abstract: Examples include techniques for improving low-density parity check decoder performance for a binary asymmetric channel in a multi-die scenario. Examples include logic for execution by circuitry to decode an encoded codeword of data received from a memory having a plurality of dies, bits of the encoded codeword stored across the plurality of dies, using predetermined log-likelihood ratios (LLRs) to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the predetermined LLRs when the decoded codeword is not correct, up to a first number of times when the decoded codeword is not correct. When a correct decoded codeword is not produced using predetermined LLRs, further logic may be executed to estimate the LLRs for a plurality of buckets of the plurality of dies, normalize magnitudes of the estimated LLRs, decode the encoded codeword using the normalized estimated LLRs to produce a decoded codeword, return the decoded codeword when the decoded codeword is correct, and repeat the decoding using the normalized estimated LLRs when the decoded codeword is not correct, up to a second number of times when the decoded codeword is not correct.