公开(公告)号：US09817738B2

公开(公告)日：2017-11-14

申请号：US14845503

申请日：2015-09-04

Applicant: Intel Corporation

Inventor： Raj K. Ramanujan ,  Camille C. Raad ,  Richard P. Mangold ,  Theodros Yigzaw

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/16 ,  G11C29/42 ,  G11C29/52 ,  G11C29/04

CPC classification number: G06F11/3037 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1612 ,  G06F11/167 ,  G06F12/00 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

Abstract: Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing the poisoned state if volatile data stored in the memory region does not correspond to a known data pattern. Additionally, the memory region may be maintained in the poisoned state if the volatile data stored in the memory region corresponds to the known data pattern. In one example, an error may be detected, wherein the error is associated with a write operation directed to the memory region. In such a case, the poisoned state may be set for the volatile data in response to the error and the known data pattern may be written to the memory region.

公开(公告)号：US09798641B2

公开(公告)日：2017-10-24

申请号：US14978597

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Robert C. Swanson ,  Theodros Yigzaw ,  Eswaramoorthi Nallusamy ,  Raghunandan Makaram ,  Vincent J. Zimmer

IPC: G06F11/00 ,  G06F11/263 ,  G06F1/24 ,  G06F21/53 ,  G06F11/10 ,  G06F11/07

CPC classification number: G06F11/263 ,  G06F1/24 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1016 ,  G06F21/53 ,  G06F2221/034

Abstract: Methods and apparatus to increase cloud availability and silicon isolation using secure enclaves. A compute platform is configured to host a compute domain in which a plurality of secure enclaves are implemented. In conjunction with creating and deploying secure enclaves, mapping information is generated that maps the secure enclaves to platform/CPU resources, such as Intellectual Property blocks (IP) belong to the secure enclaves. In response to platform error events caused by errant platform/CPU resources, the secure enclave(s) belonging to the errant platform/CPU are identified via the mapping information, and an interrupt is directed to that/those secure enclave(s). In response to the interrupt, a secure enclave may be configured to one or more of handle the error, pass information to another secure enclave, and teardown the enclave. The secure enclave may execute an interrupt service routine that causes the errant platform/CPU resource to reset without resetting the entire platform or CPU, as applicable.

公开(公告)号：US12235720B2

公开(公告)日：2025-02-25

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat Agarwal ,  Hsing-Min Chen ,  Wei P. Chen ,  Wei Wu ,  Jing Ling ,  Kuljit S. Bains ,  Kjersten E. Criss ,  Deep K. Buch ,  Theodros Yigzaw ,  John G. Holm ,  Andrew M. Rudoff ,  Vaibhav Singh ,  Sreenivas Mandava

IPC: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US12189479B2

公开(公告)日：2025-01-07

申请号：US17993591

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/14 ,  G06F11/10

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US12189468B2

公开(公告)日：2025-01-07

申请号：US17332302

申请日：2021-05-27

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  John Holm ,  Subhankar Panda ,  Hugo Enrique Gonzalez Chavero ,  Satyaprakash Nanda ,  Omar Avelar Suarez ,  Guarav Porwal

IPC: G06F11/07

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to provide management of a connected hardware subsystem with respect to one or more of reliability, availability and serviceability, and coordinate the management of the connected hardware subsystem with respect to one or more of reliability, availability and serviceability between the connected hardware subsystem and a host. Other embodiments are disclosed and claimed.

公开(公告)号：US20220334736A1

公开(公告)日：2022-10-20

申请号：US17856637

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Hsing-Min Chen ,  Theodros Yigzaw ,  Russell Clapp ,  Saravanan Sethuraman ,  Patricia Mwove Shaffer

IPC: G06F3/06

Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to apply a reliability, availability, and serviceability (RAS) policy for access to a memory in accordance with a first RAS scheme, change the applied RAS policy in accordance with a second RAS scheme at runtime, where the second RAS scheme is different from the first RAS scheme, and access the memory in accordance with the applied RAS policy. Other embodiments are disclosed and claimed.

公开(公告)号：US20210248026A1

公开(公告)日：2021-08-12

申请号：US17153337

申请日：2021-01-20

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Theodros Yigzaw ,  Murugasamy Nachimuthu ,  Ashok Raj ,  Jose Vargas

IPC: G06F11/07

Abstract: Techniques and mechanisms for a processor to efficiently identify a circuit resource as being a source of data poisoning. In an embodiment, metadata is communicated, in association with a communication of poisoned data to which the metadata pertains, to a first circuit block of a processor. The metadata indicates a poisoned state of the data, wherein the metadata identifies a second circuit block—which is included in or coupled to the processor—as being a poisoner of the data. Based on the metadata, the first circuit block generates a fault message which identifies the second circuit block as the poisoner of the data. In another embodiment, the processor further comprises the second circuit block, which poisons the data (based on the detection of an error condition) by providing in the metadata a unique identifier which is assigned to the second circuit block.

公开(公告)号：US11048587B2

公开(公告)日：2021-06-29

申请号：US16292085

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/14 ,  G06F11/10

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US10929232B2

公开(公告)日：2021-02-23

申请号：US15610067

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Subhankar Panda ,  Sarathy Jayakumar ,  Gaurav Porwal ,  Theodros Yigzaw

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/07 ,  G06F11/20

Abstract: A computing apparatus, including: a hardware platform including a processor and memory; and a system management interrupt (SMI) handler; first logic configured to provide a first container and a second container via the hardware platform; and second logic configured to: detect an uncorrectable error in the first container; responsive to the detecting, generate a degraded system state; provide a degraded state message to the SMI handler; instruct the second container to seek a recoverable state; determine that the second container has entered a recoverable state; and initiate a recovery operation.

公开(公告)号：US20190278721A1

公开(公告)日：2019-09-12

申请号：US16424875

申请日：2019-05-29

Applicant: Intel Corporation

Inventor： Ishwar Agarwal ,  Theodros Yigzaw

IPC: G06F13/16 ,  G06F12/0868 ,  G06F12/0831

Abstract: In one embodiment, an apparatus includes: a first memory controller to control access to a first memory, the first memory controller including a memory mirroring circuit, in response to a memory write request from a first processor socket for which the first memory comprises a primary memory region, to cause data associated with the memory write request to be written to the first memory and to send a shadow memory write request to a second memory to cause the second memory to write the data into a secondary memory region; and a shadow memory table including a plurality of entries each to store an association between a primary memory region and a secondary memory region. The memory mirroring circuit may access the shadow memory table to identify the secondary memory region. Other embodiments are described and claimed.