公开(公告)号：US10672701B2

公开(公告)日：2020-06-02

申请号：US15762548

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Vivek Raghunathan ,  Yonggang Li ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Johanna M. Swan

IPC: H01L23/498 ,  H01L21/48 ,  B23K26/06 ,  B23K26/36 ,  H01L21/768 ,  B23K103/16

Abstract: Discussed generally herein are methods and devices for flexible fabrics or that otherwise include thin traces. A device can include a flexible polyimide material, and a first plurality of traces on the flexible polyimide material, wherein the first plurality of traces are patterned on the flexible polyimide material using laser spallation.

公开(公告)号：US10306760B2

公开(公告)日：2019-05-28

申请号：US15497156

申请日：2017-04-25

Applicant: Intel Corporation

Inventor： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18

Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.

公开(公告)号：US20240112970A1

公开(公告)日：2024-04-04

申请号：US17957355

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Hanyu Song ,  Vinith Bejugam ,  Yonggang Li ,  Gang Duan ,  Aaron Garelick

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/73 ,  H01L2224/73204

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. A first build-up layer is on at least the first surface. In some embodiments, the corner region comprises a recess and a dielectric material within the recess. In other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. The second region comprises a second compressive stress. The first compressive stress is greater than the second compressive stress.

公开(公告)号：US20200091053A1

公开(公告)日：2020-03-19

申请号：US16131511

申请日：2018-09-14

Applicant: Intel Corporation

Inventor： Sameer Paital ,  Srinivas V. Pietambaram ,  Yonggang Li ,  Kristof Kuwawi Darmawikarta ,  Gang Duan ,  Krishna Bharath ,  Michael James Hill

IPC: H01L23/498 ,  H01F27/28 ,  H01F27/24 ,  H01F27/02 ,  H05K1/18

Abstract: Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid.

公开(公告)号：US20160322344A1

公开(公告)日：2016-11-03

申请号：US15208502

申请日：2016-07-12

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US09397079B2

公开(公告)日：2016-07-19

申请号：US14636016

申请日：2015-03-02

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.