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公开(公告)号：US11569173B2
公开(公告)日：2023-01-31
申请号：US15857752
申请日：2017-12-29
申请人： Intel Corporation
发明人： Andrew P. Collins , Digvijay A. Raorane , Wilfred Gomes , Ravindranath V. Mahajan , Sujit Sharan
IPC分类号： H01L23/538 , H01L23/48 , H01L25/065 , H01L21/48 , H01L21/50 , H01L25/18
摘要： Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.
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公开(公告)号：US20190326198A1
公开(公告)日：2019-10-24
申请号：US16457336
申请日：2019-06-28
申请人： Intel Corporation
IPC分类号： H01L23/48 , H01L23/00 , H01L25/065 , H01L25/16 , H01L21/768 , H01L23/498
摘要： An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.
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公开(公告)号：US20180345904A1
公开(公告)日：2018-12-06
申请号：US15608297
申请日：2017-05-30
申请人： Intel Corporation
CPC分类号： B60R25/01 , G07C9/00174 , G07C9/00706 , G07C9/00857 , G07C9/00896 , H04L9/3278
摘要： A user-customizable locking assembly includes a user-customizable key, a user-customizable key receiver, and a key receiver receptacle. Each of the user-customizable key, a user-customizable key receiver, and a key receiver receptacle includes a physical unclonable function (PUF) circuit configured to provide a PUF response in response to receiving a challenge signal. The PUF circuits of the user-customizable key and a user-customizable key receiver include personalization fuses that allow a user to further personalize or change the PUF response produced by the corresponding PUF circuits. The key receiver receptacle also includes anti-theft fuses, which are activated if the user-customizable key receiver is removed from the key receiver receptacle. In use, a protected system may utilize the PUF responses from the each of the PUF circuits to authenticate the user-customizable locking assembly.
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4.发明授权Thin film based electromagnetic interference shielding with BBUL/coreless packages 有权基于薄膜的电磁干扰屏蔽与BBUL /无芯封装公开(公告)号：US09232686B2
公开(公告)日：2016-01-05
申请号：US14227929
申请日：2014-03-27
申请人： INTEL CORPORATION
CPC分类号： H05K3/007 , C23C14/14 , H01L21/4857 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/49811 , H01L23/49822 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/19 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2924/1815 , H01L2924/18162 , H05K1/0219 , H05K1/185 , H05K3/02 , H05K3/30 , H05K3/4682 , H05K2201/0715 , H05K2203/1469 , H05K2203/308 , H01L2224/83 , H01L2224/82 , H01L2224/83005
摘要： An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.
摘要翻译： 一种包括模具的装置，包括具有限定模具的厚度的接触点和侧壁的装置侧; 耦合到管芯的积聚载体，所述堆积载体包括多个图案化导电材料和绝缘材料的交替层，其中图案化导电材料层中的至少一层耦合到 死; 以及包括设置在管芯上的导电材料和积聚载体的一部分的干涉屏蔽。 该装置可以连接到印刷电路板。 一种方法，包括在包括图案化导电材料和绝缘材料的多个交替层的模具的器件侧附近形成堆积载体; 以及在积聚载体的一部分上形成干涉屏蔽。
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公开(公告)号：US11049798B2
公开(公告)日：2021-06-29
申请号：US16457336
申请日：2019-06-28
申请人： Intel Corporation
IPC分类号： H01L23/48 , H01L23/49 , H01L21/76 , H01L21/768 , H01L23/498 , H01L23/00 , H01L25/16 , H01L23/538 , H01L25/065
摘要： An integrated circuit (IC) package comprising a-substrate having a first side and an opposing a second side, and a bridge die within the substrate. The bridge die comprises a plurality of vias extending from a first side to a second side of the-bridge die. The-bridge die comprises a first plurality of pads on the first side of the bridge die and a second plurality of pads on the second side. The plurality of vias interconnect snes of the first plurality of pads to ones of the second plurality of pads. The bridge die comprises an adhesive film over a layer of silicon oxide on the second side of the bridge die.
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公开(公告)号：US20200098655A1
公开(公告)日：2020-03-26
申请号：US16619061
申请日：2017-06-30
申请人： Intel Corporation
发明人： Vijay K. Nair , Digvijay A. Raorane
IPC分类号： H01L23/10 , H01L23/498 , H01L23/055 , H01L23/552 , H01L23/367 , H01L21/48 , H01L23/31 , H01L25/065 , H01L23/538
摘要： Enclosure technology for electronic components is disclosed. An enclosure for an electronic component can comprise a base member and a cover member disposed on the base member such that the cover member and the base member form an enclosure for an electronic component. In one aspect, the base member can have at least one via extending therethrough. The at least one via can be configured to electrically couple an enclosed electronic component with another electronic component external to the enclosure. In another aspect, the cover member can include a protrusion, a receptacle, or both, and the base member can include a mating protrusion, receptacle, or both to facilitate proper alignment of the cover member and the base member. Electronic device packages and associated systems and methods are also disclosed.
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公开(公告)号：US20190311983A1
公开(公告)日：2019-10-10
申请号：US16462908
申请日：2016-12-27
申请人： Intel Corporation
IPC分类号： H01L23/522 , H01L25/18 , H01L23/00 , H01L23/528 , H01L23/48 , H01L21/768
摘要： An apparatus is provided comprising: first die, wherein a first plurality of interconnect structures is formed on the first die; one or more layers, wherein a first surface of the one or more layers is attached to the first plurality of interconnect structures; a second plurality of interconnect structures formed on a second surface of the one or more layers; and a second die, wherein a third plurality of interconnect structures is formed on the second die, wherein a first interconnect structure of the first plurality of interconnect structures is electrically connected to a second interconnect structure of the second plurality of interconnect structures through the one or more layers, and wherein the first die is mounted on the second die such that the second interconnect structure of the second plurality of interconnect structures is attached to a third interconnect structure of the third plurality of interconnect structures.
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公开(公告)号：US20190287956A1
公开(公告)日：2019-09-19
申请号：US16464665
申请日：2016-12-30
申请人： Intel Corporation
IPC分类号： H01L25/18 , H01L23/31 , H01L23/48 , H01L23/522 , H01L21/56 , H01L21/768
摘要： An apparatus is provided comprising: a substrate; a die having a first side and a second side, wherein the die is mounted on the substrate such that the first side of the die faces the substrate, and wherein at least a portion of the first side of the die is removed to form a recess in the die; and a component, wherein at least a part of the component is disposed within the recess in the first die.
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公开(公告)号：US20190006264A1
公开(公告)日：2019-01-03
申请号：US15640406
申请日：2017-06-30
申请人： Intel Corporation
IPC分类号： H01L23/48 , H01L21/768 , H01L23/498 , H01L23/00 , H01L25/16
CPC分类号： H01L23/481 , H01L21/76898 , H01L23/49827 , H01L24/06 , H01L24/09 , H01L24/83 , H01L25/0655 , H01L25/16 , H01L2224/16225
摘要： An apparatus comprising: a substrate having a first side opposing a second side, and comprises a first conductive layer disposed on the first side of the package substrate, and a second conductive layer disposed between the first side and the second side of the package substrate, the substrate having dielectric material disposed between the first conductive layer and the second conductive layer; and at least one at least one bridge die disposed within the substrate, the at least one bridge die having a first side opposing a second side, and comprising a plurality of vias extending from the first side to the second side of the at least one bridge die, wherein the second conductive layer disposed between the first and second sides of the substrate is coupled to the plurality of vias extending from the first side of the at least one bridge die to the second side of the at least one bridge die.
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公开(公告)号：US10421432B2
公开(公告)日：2019-09-24
申请号：US15608297
申请日：2017-05-30
申请人： Intel Corporation
摘要： A user-customizable locking assembly includes a user-customizable key, a user-customizable key receiver, and a key receiver receptacle. Each of the user-customizable key, a user-customizable key receiver, and a key receiver receptacle includes a physical unclonable function (PUF) circuit configured to provide a PUF response in response to receiving a challenge signal. The PUF circuits of the user-customizable key and a user-customizable key receiver include personalization fuses that allow a user to further personalize or change the PUF response produced by the corresponding PUF circuits. The key receiver receptacle also includes anti-theft fuses, which are activated if the user-customizable key receiver is removed from the key receiver receptacle. In use, a protected system may utilize the PUF responses from the each of the PUF circuits to authenticate the user-customizable locking assembly.
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