公开(公告)号：US09082625B2

公开(公告)日：2015-07-14

申请号：US14102873

申请日：2013-12-11

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Yiheng Xu ,  John Zhang

IPC: B44C1/22 ,  H01L21/033 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L21/0337 ,  B81C1/0046 ,  G03F7/0002 ,  H01L21/31144

Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

Abstract translation: 本发明的实施例提供一种形成装置图案的方法。 该方法包括定义要在设备层中创建的设备图案; 在器件层的顶部上形成牺牲层; 识别在其高度的位置处具有表示装置图案的水平横截面形状的压印模具; 将压印模均匀地推入牺牲层，直到至少压印模具的位置达到被压印模推送的牺牲层内的水平面; 将所述压印模具远离所述牺牲层移除; 在由牺牲层中的压印模制成的凹部中形成硬掩模，硬掩模具有表示装置图案的图案; 并将硬掩模的图案转移到器件层的下方。

公开(公告)号：US20150162194A1

公开(公告)日：2015-06-11

申请号：US14102873

申请日：2013-12-11

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Carl J. Radens ,  Richard S. Wise ,  Yiheng Xu ,  John Zhang

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/0337 ,  B81C1/0046 ,  G03F7/0002 ,  H01L21/31144

Abstract: Embodiments of present invention provide a method of forming device pattern. The method includes defining a device pattern to be created in a device layer; forming a sacrificial layer on top of the device layer; identifying an imprinting mold that, at a position along a height thereof, has a horizontal cross-sectional shape that represents the device pattern; pushing the imprinting mold uniformly into the sacrificial layer until at least the position of the imprinting mold reaches a level inside the sacrificial layer that is being pushed by the imprinting mold; removing the imprinting mold away from the sacrificial layer; forming a hard mask in recesses created by the imprinting mold in the sacrificial layer, the hard mask has a pattern representing the device pattern; and transferring the pattern of the hard mask into underneath the device layer.

Abstract translation: 本发明的实施例提供一种形成装置图案的方法。 该方法包括定义要在设备层中创建的设备模式; 在器件层的顶部上形成牺牲层; 识别在其高度的位置处具有表示装置图案的水平横截面形状的压印模具; 将压印模均匀地推入牺牲层，直到至少压印模具的位置达到被压印模推送的牺牲层内的水平面; 将所述压印模具远离所述牺牲层移除; 在由牺牲层中的压印模制成的凹部中形成硬掩模，硬掩模具有表示装置图案的图案; 并将硬掩模的图案转移到器件层的下方。

公开(公告)号：US20150076695A1

公开(公告)日：2015-03-19

申请号：US14027556

申请日：2013-09-16

Applicant: International Business Machines Corporation

Inventor： Tien-Jen Cheng ,  Lawrence A. Clevenger ,  Terence L. Kane ,  Carl J. Radens ,  Andrew H. Simon ,  Yun-Yu Wang ,  Yiheng Xu ,  John Zhang

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated circuit structure includes forming a cap layer above a first ILD layer of a first metal level, the first ILD layer includes a recess filled with a first conductive material to form a first interconnect structure. Next, a second ILD layer is formed above the cap layer and a via is formed within the second ILD layer as a second interconnect structure of a second metal level. The via is aligned with the first interconnect structure. Subsequently, a portion of the cap layer is removed to extend the via to expose a top portion of the first conductive material then a passivation cap is selectively formed at a bottom portion of the via in the second ILD layer and the passivation cap contacting the top portion of the first conductive material. The passivation cap includes a metal alloy to form an interface between the bottom portion of the via and the first conductive material.

Abstract translation: 形成集成电路结构的方法包括在第一金属层的第一ILD层上形成覆盖层，第一ILD层包括填充有第一导电材料以形成第一互连结构的凹陷。 接下来，在盖层之上形成第二ILD层，并且在第二ILD层内形成通孔作为第二金属层的第二互连结构。 通孔与第一互连结构对准。 随后，去除盖层的一部分以延伸通孔以暴露第一导电材料的顶部部分，然后在第二ILD层中的通孔的底部选择性地形成钝化帽，并且钝化帽接触顶部 第一导电材料的一部分。 钝化盖包括金属合金，以形成通孔的底部与第一导电材料之间的界面。

公开(公告)号：US20140215274A1

公开(公告)日：2014-07-31

申请号：US14242418

申请日：2014-04-01

Applicant: International Business Machines Corporation

Inventor： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Carl J. Radens

IPC: G06F11/00

CPC classification number: G06F11/076 ,  G06F11/008 ,  G06F11/079 ,  G06F17/5009 ,  G06F17/5022 ,  G06F2217/10

Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

Abstract translation: 提供了一种用于重用采样的机制，用于有效地进行细胞故障率估计过程变化和其他设计考虑。 首先，该机制对电路参数进行搜索，以确定相对于一组性能变量的故障。 对于单个故障区域，初始搜索可以是参数空间的均匀采样。 混合重要性抽样（MIS）有效地估计单个故障区域。 然后，该机制找到每个度量的重心，并发现重要性样本。 然后，对于对应于过程变化或其他设计考虑的每个新的原点，机制找到合适的投影并重新计算新的重要性抽样（IS）比率。

公开(公告)号：US20140170844A1

公开(公告)日：2014-06-19

申请号：US14167532

申请日：2014-01-29

Applicant: International Business Machines Corporation

Inventor： Michael P. Chudzik ,  Dechao Guo ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Carl J. Radens ,  Shahab Siddiqui

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092

Abstract: A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) is provided. Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack may also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N2 and an nFET threshold voltage adjusted species located therein.

Abstract translation: 提供包括缩放的n沟道场效应晶体管（nFET）和缩放的p沟道场效应晶体管（pFET）的互补金属氧化物半导体（CMOS）结构。 通过在nFET栅极堆叠内形成等离子体氮化的nFET阈值电压调整的高k栅极电介质层部分，以及在pFET栅极堆叠内形成至少pFET阈值电压调整的高k栅介质层部分来提供这种结构。 pFET栅极堆叠中的pFET阈值电压调节的高k栅介质层部分也可以等离子体氮化。 等离子体氮化nFET阈值电压调节的高k栅极电介质层部分包括高达15原子％的N 2和位于其中的nFET阈值电压调节的物质。

公开(公告)号：US08629028B2

公开(公告)日：2014-01-14

申请号：US13773881

申请日：2013-02-22

Applicant: International Business Machines Corporation

Inventor： Christopher V. Baiocco ,  Daniel J. Jaeger ,  Carl J. Radens ,  Helen Wang

IPC: H01L21/336

CPC classification number: H01L29/7816 ,  H01L21/28247 ,  H01L29/0642 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

Abstract: A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure.

公开(公告)号：US20130270224A1

公开(公告)日：2013-10-17

申请号：US13912591

申请日：2013-06-07

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Elbert E. Huang ,  Sampath Purushothaman ,  Carl J. Radens

IPC: H05K3/40

CPC classification number: H05K3/40 ,  H01B17/66 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76822 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T156/1039 ,  Y10T156/1082 ,  Y10T428/24521 ,  Y10T428/24529 ,  Y10T428/24537 ,  Y10T428/24612 ,  Y10T428/24711 ,  H01L2924/00

Abstract: Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.

公开(公告)号：US20130143377A1

公开(公告)日：2013-06-06

申请号：US13752567

申请日：2013-01-29

Applicant: International Business Machines Corporation

Inventor： Shahab Siddiqui ,  Michael P. Chudzik ,  Carl J. Radens

IPC: H01L29/66

CPC classification number: H01L29/66575 ,  H01L21/28088 ,  H01L21/76897 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

Abstract translation: 本公开提供了一种用于形成半导体器件的方法，其包括形成覆盖在衬底的沟道区上的替代栅极结构。 在衬底的源极和漏极区域上形成心轴介电层。 去除替代栅极结构以提供暴露衬底的沟道区的开口。 在包括功函数金属层的沟道区域上形成功能栅极结构。 在功能栅极结构上形成保护帽结构。 通过对保护盖结构有选择性的心轴介质层蚀刻至少一个通孔，以暴露源极区域和漏极区域中的至少一个的一部分。 然后在通孔中形成导电填充物以提供与源极区域和漏极区域中的至少一个的接触。

公开(公告)号：US11372701B2

公开(公告)日：2022-06-28

申请号：US16543776

申请日：2019-08-19

Applicant: International Business Machines Corporation

Inventor： Rajiv V. Joshi ,  Rouwaida N. Kanj ,  Sani R. Nassif ,  Carl J. Radens

IPC: G06F30/33 ,  G06F30/20 ,  G06F111/08 ,  G06F11/07 ,  G06F11/00

Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

公开(公告)号：US11348832B2

公开(公告)日：2022-05-31

申请号：US16460250

申请日：2019-07-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin C. Backes ,  Brian A. Cohen ,  Joyeeta Nag ,  Carl J. Radens

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/288 ,  H01L21/311 ,  H01L23/528

Abstract: A self-aligned via interconnect structures and methods of manufacturing thereof are disclosed. The method includes forming a wiring structure in a dielectric material. The method further includes forming a cap layer over a surface of the wiring structure and the dielectric material. The method further includes forming an opening in the cap layer to expose a portion of the wiring structure. The method further includes selectively growing a metal or metal-alloy via interconnect structure material on the exposed portion of the wiring structure, through the opening in the cap layer. The method further includes forming an upper wiring structure in electrical contact with the metal or metal-alloy via interconnect structure.