公开(公告)号：US20240074336A1

公开(公告)日：2024-02-29

申请号：US17894549

申请日：2022-08-24

Applicant: International Business Machines Corporation

Inventor： Injo Ok ,  Timothy Mathew Philip ,  Jin Ping Han ,  Ching-Tzu Chen ,  Kevin W. Brew ,  Lili Cheng

IPC: H01L45/00

CPC classification number: H01L45/126 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

Abstract: A memory device and method of forming a projection liner under a mushroom phase change memory device with sidewall electrode process scheme to provide self-aligned patterning of resistive projection liner during sidewall electrode formation.

公开(公告)号：US10468432B1

公开(公告)日：2019-11-05

申请号：US15992960

申请日：2018-05-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jin Ping Han ,  Ramachandran Muralidhar ,  Paul M. Solomon ,  Dennis M. Newns ,  Martin M. Frank

IPC: H01L27/1159 ,  H01L27/11585 ,  G11C11/56 ,  H01L27/24 ,  G11C11/22 ,  H01L27/11587

Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.

公开(公告)号：US20190326387A1

公开(公告)日：2019-10-24

申请号：US16502783

申请日：2019-07-03

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L49/02 ,  H01B3/10 ,  H01L27/11507 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/283

Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

公开(公告)号：US20190252500A1

公开(公告)日：2019-08-15

申请号：US16395084

申请日：2019-04-25

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L29/12 ,  H01L23/52 ,  H01L29/06 ,  H01L27/085

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US10381431B2

公开(公告)日：2019-08-13

申请号：US15797848

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L27/11507 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/283 ,  H01B3/10

Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.

公开(公告)号：US10381061B2

公开(公告)日：2019-08-13

申请号：US15717023

申请日：2017-09-27

Applicant: International Business Machines Corporation

Inventor： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC: G06N3/06 ,  G11C11/22 ,  H03K19/177

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US10319818B2

公开(公告)日：2019-06-11

申请号：US15797774

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L29/12 ,  H01L29/06 ,  H01L27/085 ,  H01L23/52

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US20190131407A1

公开(公告)日：2019-05-02

申请号：US15797774

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L29/12 ,  H01L23/52 ,  H01L27/085 ,  H01L29/06

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US20190096463A1

公开(公告)日：2019-03-28

申请号：US15859583

申请日：2017-12-31

Applicant: International Business Machines Corporation

Inventor： Jin Ping Han ,  Xiao Sun ,  Teng Yang

IPC: G11C11/22 ,  H03K19/177

CPC classification number: G11C11/223 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2259 ,  G11C11/2275 ,  G11C11/54 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5657 ,  G11C11/5671 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H03K19/1776

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

公开(公告)号：US10229984B2

公开(公告)日：2019-03-12

申请号：US15856518

申请日：2017-12-28

Applicant: International Business Machines Corporation

Inventor： Victor Chan ,  Jin Ping Han ,  Shangbin Ko

IPC: H01L21/283 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/225 ,  H01L23/535

Abstract: A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack.