公开(公告)号：US20180248555A1

公开(公告)日：2018-08-30

申请号：US15445587

申请日：2017-02-28

Applicant: International Business Machines Corporation

Inventor： Keith A. Jenkins ,  Peilin Song ,  James H. Stathis ,  Franco Stellari

IPC: H03L1/00 ,  H03K3/03

CPC classification number: H03L1/00 ,  G01R31/2824 ,  G01R31/2851 ,  H03B1/00 ,  H03B5/12 ,  H03B5/1215 ,  H03B5/30 ,  H03B5/36 ,  H03K3/0315 ,  H04L9/3278

Abstract: An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.

公开(公告)号：US20180246159A1

公开(公告)日：2018-08-30

申请号：US15443688

申请日：2017-02-27

Applicant: International Business Machines Corporation

Inventor： Tam N. Huynh ,  Keith A. Jenkins ,  Franco Stellari

IPC: G01R31/12 ,  G01R31/26 ,  H03K3/03

CPC classification number: G01R31/129 ,  G01R31/14 ,  G01R31/3008 ,  H03K3/0315

Abstract: A method and system of monitoring a reliability of a semiconductor circuit are provided. A current consumption of a first ring oscillator that is in static state is measured at predetermined intervals. Each measured current consumption value is stored. A baseline current consumption value of the first ring oscillator is determined based on the stored current consumption values. A latest measured current consumption value of the first ring oscillator is compared to the baseline current consumption value. Upon determining that the latest measured current consumption value is above a threshold deviation from the baseline current consumption value, the first ring oscillator is identified to have a dielectric breakdown degradation.

公开(公告)号：US20180211894A1

公开(公告)日：2018-07-26

申请号：US15925989

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith A. Jenkins ,  Barry Linder

IPC: H01L21/66

CPC classification number: H01L22/34 ,  G01R31/2642 ,  G01R31/2884

Abstract: Methods and circuits for monitoring circuit degradation include measuring degradation in a set of on-chip test oscillators that vary according to a quantity that influences a first type of degradation. A second type of contribution to the measured degradation is determined by extrapolating from the measured degradation for the plurality of test oscillators. The second type of contribution is subtracted from the measured degradation at a predetermined value of the quantity to determine the first type of degradation for devices represented by the predetermined value.

公开(公告)号：US10002810B2

公开(公告)日：2018-06-19

申请号：US14750748

申请日：2015-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith A. Jenkins ,  Barry Linder

IPC: G01R31/26 ,  G01R31/28 ,  H01L21/66

CPC classification number: H01L22/34 ,  G01R31/2642 ,  G01R31/2884

Abstract: Methods and circuits for monitoring circuit degradation include measuring degradation in a plurality of on-chip test oscillators that vary according to a quantity that influences hot carrier injection (HCI) degradation. The measured degradation for the plurality of test oscillators is extrapolated to determine a bias temperature instability (BTI) contribution to the measured degradation. The BTI contribution is subtracted from the measured degradation at a predetermined value of the quantity to determine the HCI degradation for devices represented by the predetermined value.

公开(公告)号：US20180035298A1

公开(公告)日：2018-02-01

申请号：US15725691

申请日：2017-10-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith A. Jenkins ,  Barry P. Linder

IPC: H04W12/08 ,  H04L29/06

CPC classification number: H04W12/08 ,  G06F21/36 ,  G06F21/629 ,  H04L63/102

Abstract: A method for gaining access beyond a restricted access gateway includes an access key sequence stored on memory of a device. The access key sequence includes a sequence of key entries and key touch movements. An entered request sequence including keys activated by touch on a keyboard of the device and directions of touch movements made on the keyboard is recorded. With an access controller, it is determined whether the recorded entered request sequence matches the access key sequence. Access beyond the restricted access gateway is granted to functions when the recorded entered request sequence matches the access key sequence.

公开(公告)号：US20170329685A1

公开(公告)日：2017-11-16

申请号：US15156136

申请日：2016-05-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith A. Jenkins ,  Barry P. Linder ,  Emily A. Ray ,  Raphael P. Robertazzi ,  Peilin Song ,  James H. Stathis ,  Kevin G. Stawiasz ,  Franco Stellari ,  Alan J. Weger ,  Emmanuel Yashchin

IPC: G06F11/22 ,  G06F11/263

CPC classification number: G06F11/2236 ,  G06F11/008 ,  G06F11/24

Abstract: A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.

公开(公告)号：US09791499B2

公开(公告)日：2017-10-17

申请号：US14602544

申请日：2015-01-22

Applicant: International Business Machines Corporation

Inventor： Keith A. Jenkins ,  Barry P. Linder ,  Kevin G. Stawiasz

IPC: G01R31/26 ,  G01R31/28 ,  G06F11/00 ,  G01R31/02 ,  H01L21/66

CPC classification number: G01R31/2853 ,  G01R31/026 ,  G01R31/2856 ,  G01R31/2858 ,  G06F11/00 ,  H01L22/34

Abstract: A test structure and method to detect open circuits due to electromigration or burn-out in test wires and inter-level vias. Electromigration occurs when current flows through circuit wires leading to a circuit interruption within the wire. The test structure is a passive test wire arranged in one of several configurations within the circuit of a computer chip. The dimensions and resistances of test wires can vary according to the test structure configuration. Each test wire is measured for an electrical discontinuity after the computer chip is powered-on. If a wiring interruption is detected, it is concluded that the chip had been powered-on before.

公开(公告)号：US20170269152A1

公开(公告)日：2017-09-21

申请号：US15070577

申请日：2016-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith A. Jenkins ,  Siyuranga O. Koswatta

IPC: G01R31/28 ,  H02H1/00

CPC classification number: G01R31/2858 ,  H02H1/0007

Abstract: Embodiments include methods, and systems of an integrated circuit having electromigration wearout detection circuits. Integrated circuit may include a detection element and a reference element. Detection element is subject to normal operation current. Reference element is not subject to normal operation current. A resistance of detection element is monitored to detect electromigration wearout. The electromigration wearout detection monitoring circuit may be configured to perform: periodically measuring resistance of detection element, calculating resistance change of detection element over a predetermined time period, comparing resistance change of detection element calculated to a predetermined safety threshold, and take mitigation actions when resistance change of detection element exceeds predetermined safety threshold. The mitigation actions may include switching to a redundant circuit of the integrated circuit, shutting down the integrated circuit, and sending a signal to initiate a service call. The predetermined safety threshold may be 1% of resistance change of the detection element.

公开(公告)号：US20160266195A1

公开(公告)日：2016-09-15

申请号：US14657437

申请日：2015-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Keith A. Jenkins ,  Barry P. Linder

IPC: G01R31/26 ,  G01R31/02

CPC classification number: G01R31/2628 ,  G01R31/025 ,  G01R31/2601 ,  G01R31/2648

Abstract: A method of measuring semiconductor output characteristics is provided that includes connecting a pulse generator to the gate structure of a semiconductor device, and applying a plurality of voltage pulses at least some of which having a different pulse width to the gate structure of the semiconductor device. The average current is measured from the drain structure of the device for a duration of each pulse of the plurality of pulses. From the measured values for the average current, a self-heating curve of the average current divided by the pulse width is plotted as a function of the pulse width. The self-heating curve is then extrapolated to a pulse width substantially equal to zero to provide a value of drain current measurements without self-heating effects.

公开(公告)号：US11105856B2

公开(公告)日：2021-08-31

申请号：US16189295

申请日：2018-11-13

Applicant: International Business Machines Corporation

Inventor： Emily A. Ray ,  Emmanuel Yashchin ,  Peilin Song ,  Kevin G. Stawiasz ,  Barry Linder ,  Alan Weger ,  Keith A. Jenkins ,  Raphael P. Robertazzi ,  Franco Stellari ,  James Stathis

IPC: G06F11/22 ,  G01R31/3193 ,  G01R31/319

Abstract: Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.