公开(公告)号：US10553493B2

公开(公告)日：2020-02-04

申请号：US16046273

申请日：2018-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.

公开(公告)号：US10541330B2

公开(公告)日：2020-01-21

申请号：US16031142

申请日：2018-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xin Miao ,  Peng Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L27/112 ,  H01L27/24 ,  H01L29/08

Abstract: A method of making a vertical transistor device includes forming a front gate and a back gate opposite a major surface of a substrate. The front gate and the back gate are symmetric and arranged on opposing sides of a channel between the front gate and the back gate. The channel extends from a drain to a source. The method includes disposing a mask to cover the front gate and removing the back gate. The method further includes replacing the back gate with a layer of insulator and another back gate stack. The another back gate stack only covers a junction between the channel and the source, and remaining portions of the back gate are the layer of insulator.

公开(公告)号：US10522661B2

公开(公告)日：2019-12-31

申请号：US15926151

申请日：2018-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao Li ,  Xin Miao

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/786 ,  H01L27/12

Abstract: Methods of forming a semiconductor device include forming stress liners in contact with both ends of a fin of alternating channel material and sacrificial material layers. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack on the suspended layers of channel material.

公开(公告)号：US20190393343A1

公开(公告)日：2019-12-26

申请号：US16553812

申请日：2019-08-28

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Shogo Mochizuki ,  Jingyun Zhang ,  Xin Miao

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

公开(公告)号：US20190355833A1

公开(公告)日：2019-11-21

申请号：US15980111

申请日：2018-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Wenyu Xu

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/225 ,  H01L29/10 ,  H01L29/78

Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

公开(公告)号：US10483375B1

公开(公告)日：2019-11-19

申请号：US16037305

申请日：2018-07-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Wenyu Xu ,  Chen Zhang ,  Kangguo Cheng ,  Xin Miao

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/306 ,  H01L29/04 ,  H01L21/3105 ,  H01L21/02

Abstract: A method for fabricating a semiconductor device including a vertical transistor includes forming a fin structure from a substrate. The fin structure includes a fin. The method further includes forming a bottom source/drain region on the substrate adjacent to the fin, etching a longitudinal end portion of the fin to create a gap exposing the substrate, forming a gate and a top source/drain region, and forming a contact wrapping around a horizontal portion and a vertical portion of the bottom source/drain region in a region including a location where the longitudinal end portion of the fin was removed by the etching.

公开(公告)号：US10468524B2

公开(公告)日：2019-11-05

申请号：US15468300

申请日：2017-03-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Philip J. Oldiges ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06

Abstract: Provided is a method for forming a semiconductor structure. In embodiments of the invention, the method includes forming a semiconductor fin on a source/drain region, forming a liner including a first dielectric material along sidewalls of the semiconductor fin and along sidewalls of the source/drain region, forming a second dielectric material along sidewalls of the liner including the first dielectric material, and removing the liner including the first dielectric material from sidewalls of the semiconductor fin. Removing the liner including the first dielectric material includes exposing portions of the source/drain region. The method further includes forming a spacer layer on the second dielectric material and portions of the source/drain region exposed by removing the liner including the first dielectric material and forming a gate material on the spacer layer.

公开(公告)号：US10439063B2

公开(公告)日：2019-10-08

申请号：US15888745

申请日：2018-02-05

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Shogo Mochizuki ,  Jingyun Zhang ,  Xin Miao

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265

Abstract: A self-limiting etch is used to provide a semiconductor base located between a semiconductor substrate and a semiconductor fin. The semiconductor base has an upper portion, a lower portion and a midsection. The midsection has a narrower width than the lower and upper portions. A bottom source/drain structure is grown from surfaces of the semiconductor substrate and the semiconductor base. The bottom source/drain structure has a tip region that contacts the midsection of the semiconductor base. The bottom source/drain structures on each side of the semiconductor fin are in close proximity to each other and they have increased volume. Reduced access resistance may also be achieved since the bottom source/drain structure has increased volume.

公开(公告)号：US10411114B2

公开(公告)日：2019-09-10

申请号：US15851149

申请日：2017-12-21

Applicant: International Business Machines Corporation

Inventor： Chen Zhang ,  Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Peng Xu

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L21/28 ,  H01L21/02

Abstract: Semiconductor devices and methods are provided to fabricate FET devices. For example, a semiconductor device can include a functional gate structure on a channel region of a fin structure; and a source/drain region on each side of the functional gate structure. The functional gate structure has an insulator material abutting a portion of the sidewalls of the functional gate structure and the source drain region and the top surface of the fin, with a top surface of the insulator material in contact with a bottom surface of the first spacer layer. The functional gate structure further includes a dielectric top layer. The dielectric top layer seals an air gap between the top surface of the insulator material and the dielectric top layer.

公开(公告)号：US10395922B2

公开(公告)日：2019-08-27

申请号：US15832119

申请日：2017-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.