公开(公告)号：US09679967B1

公开(公告)日：2017-06-13

申请号：US15282152

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Kevin K. Chan ,  John Rozen ,  Jeng-Bang Yau ,  Yu Zhu

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/266 ,  H01L21/02 ,  H01L21/225 ,  H01L29/207

CPC classification number: H01L21/823418 ,  H01L21/02241 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/18 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/28575 ,  H01L21/3215 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/452 ,  H01L29/66007 ,  H01L29/66522 ,  H01L29/6659 ,  H01L29/66628

Abstract: A method for forming a semiconductor device includes forming a III-V semiconductor substrate and forming a gate structure on the III-V semiconductor substrate. The method also includes forming a thin spacer surrounding the gate structure and forming a source/drain junction with a first doped III-V material at an upper surface of the III-V semiconductor substrate. The method also includes oxidizing a surface the source/drain forming an oxidation layer; removing natural oxides from the oxidation layer on a surface of the source/drain to expose ions of the first doped material at least at a surface of the source/drain. The method further includes applying a second doping to the source/drain to increase a doping concentration of the first doped III-V material, forming metal contacts at least at the second doped surface of the source/drain; and then annealing the contact.

公开(公告)号：US09287426B1

公开(公告)日：2016-03-15

申请号：US14499788

申请日：2014-09-29

Applicant: International Business Machines Corporation

Inventor： Nestor A. Bojarczuk ,  Talia S. Gershon ,  Supratik Guha ,  Byungha Shin ,  Yu Zhu

IPC: H01L31/18 ,  H01L31/032 ,  H01L31/0368

CPC classification number: H01L31/0326 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02483 ,  H01L21/02488 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02568 ,  H01L21/02609 ,  H01L21/02631 ,  H01L21/02658 ,  Y02E10/50

Abstract: Techniques for epitaxial growth of CZT(S,Se) materials on Si are provided. In one aspect, a method of forming an epitaxial kesterite material is provided which includes the steps of: selecting a Si substrate based on a crystallographic orientation of the Si substrate; forming an epitaxial oxide interlayer on the Si substrate to enhance wettability of the epitaxial kesterite material on the Si substrate, wherein the epitaxial oxide interlayer is formed from a material that is lattice-matched to Si; and forming the epitaxial kesterite material on a side of the epitaxial oxide interlayer opposite the Si substrate, wherein the epitaxial kesterite material includes Cu, Zn, Sn, and at least one of S and Se, and wherein a crystallographic orientation of the epitaxial kesterite material is based on the crystallographic orientation of the Si substrate. A method of forming an epitaxial kesterite-based photovoltaic device and an epitaxial kesterite-based device are also provided.

Abstract translation: 提供了在Si上CZT（S，Se）材料外延生长的技术。 一方面，提供一种形成外延硅藻土材料的方法，其包括以下步骤：基于Si衬底的晶体取向选择Si衬底; 在Si衬底上形成外延氧化物中间层，以增强外延硅藻土材料在Si衬底上的润湿性，其中外延氧化物中间层由与Si晶格匹配的材料形成; 以及在与Si衬底相对的外延氧化物层的一侧上形成外延硅藻土材料，其中所述外延硅藻土材料包括Cu，Zn，Sn以及S和Se中的至少一种，并且其中外延硅藻土材料的晶体取向 是基于Si衬底的晶体取向。 还提供了一种形成外延的基于硅藻土的光电器件和基于外延硅藻土的器件的方法。

公开(公告)号：US08772906B2

公开(公告)日：2014-07-08

申请号：US13948166

申请日：2013-07-22

Applicant: International Business Machines Corporation

Inventor： Matthew J. BrightSky ,  Roger W. Cheek ,  Chung H. Lam ,  Eric A. Joseph ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

IPC: H01L23/52

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material.

Abstract translation: 用于相变存储器的存储单元结构。 包括由导电材料构成的底部电极和设置在底部电极上方的相变材料的示例性存储单元结构。 至少部分地，在底部电极和相变材料之间设置绝热材料层。 绝热材料由氧化钽组成。 顶部电极由导电材料构成。

公开(公告)号：US20130299768A1

公开(公告)日：2013-11-14

申请号：US13948166

申请日：2013-07-22

Applicant: International Business Machines Corporation

Inventor： Matthew J. BrightSky ,  Roger W. Cheek ,  Chung H. Lam ,  Eric A. Joseph ,  Bipin Rajendran ,  Alejandro G. Schrott ,  Yu Zhu

IPC: H01L45/00

CPC classification number: H01L45/06 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: Memory cell structures for phase change memory. An example memory cell structure comprising includes a bottom electrode comprised of electrically conducting material, and phase change material disposed above the bottom electrode. A layer of thermally insulating material is disposed, at least partially, between the bottom electrode and the phase change material. The thermally insulating material is comprised of Tantalum Oxide. A top electrode is comprised of electrically conducting material.

Abstract translation: 用于相变存储器的存储单元结构。 包括由导电材料构成的底部电极和设置在底部电极上方的相变材料的示例性存储单元结构。 至少部分地，在底部电极和相变材料之间设置绝热材料层。 绝热材料由氧化钽组成。 顶部电极由导电材料构成。

公开(公告)号：US20240386657A1

公开(公告)日：2024-11-21

申请号：US18197327

申请日：2023-05-15

Applicant: International Business Machines Corporation

Inventor： Peng Hui Jiang ,  Jun Su ,  Su Liu ,  Yu Zhu ,  Guang Han Sui

IPC: G06T17/00 ,  A61B5/16 ,  G06V40/16

Abstract: Mechanisms are provided for personalizing a computer generated virtual environment. Sensors associated with a user collect emotion data representing physiological conditions of the user in response to stimuli. Source computing systems collect stimuli context data and the stimuli context data is correlated with the emotion data. Machine learning model(s) are trained, based on the emotion data and correlated stimuli context data, to predict an emotion of the user from patterns of input data. Runtime emotion data is received from the sensors, and runtime stimuli context data is received from a virtual environment provider computing system for a computer generated virtual environment. The trained machine learning model(s) generate a predicted emotion of the user based on the runtime emotion data and the runtime stimuli context data. In cases, the virtual environment is modified based on the predicted emotion of the user.

公开(公告)号：US20240362867A1

公开(公告)日：2024-10-31

申请号：US18139253

申请日：2023-04-25

Applicant: International Business Machines Corporation

Inventor： Guang Han Sui ,  Peng Hui Jiang ,  Jun Su ,  Su Liu ,  Yu Zhu

IPC: G06T19/00

CPC classification number: G06T19/006 ,  G06T19/003

Abstract: A computer-implemented method, according to one embodiment, includes outputting, from a first user device associated with a first user that owns a first portion of land in a metaverse to a second user device associated with a second user that owns a second portion of land in the metaverse, a first request for being defined as a first neighbor of the first user. In response to a determination that an acceptance has been received from the second user device to be defined as the first neighbor of the first user, an adapter is caused to be added to a sub-portion of the first portion of land and a sub-portion of the second portion of land. The method further includes generating a definition of neighbors of the first portion of land, the definition including the first neighbor. The definition is caused to be recorded in a predetermined database.

公开(公告)号：US10559666B2

公开(公告)日：2020-02-11

申请号：US16247989

申请日：2019-01-15

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy M. Cohen ,  Amlan Majumdar ,  Yu Zhu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/205 ,  H01L21/762 ,  H01L21/02

Abstract: A structure includes a semiconductor substrate, a semiconductor buffer layer disposed over the semiconductor substrate, an oxide layer disposed over the buffer layer, and a fin including a semiconductor material disposed over the oxide layer. The semiconductor material has an oxidation rate different from an oxidation rate of the buffer layer.

公开(公告)号：US20190311945A1

公开(公告)日：2019-10-10

申请号：US16443283

申请日：2019-06-17

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Sebastian U. Engelmann ,  Marinus Johannes Petrus Hopstaken ,  Christopher Scerbo ,  Hongwen Yan ,  Yu Zhu

IPC: H01L21/768 ,  H01L21/223 ,  H01L23/535 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78 ,  H01L21/285 ,  H01L21/28

Abstract: After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.

公开(公告)号：US20190304541A1

公开(公告)日：2019-10-03

申请号：US16290353

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Wanki Kim ,  Chung Hon Lam ,  Yu Zhu ,  Yujun Xie

IPC: G11C13/00 ,  H01L45/00 ,  H01L21/66

Abstract: Techniques for void reduction in phase change memory (PCM) devices are provided. In one embodiment, the system is provided that comprises a PCM device comprising a first electrode and a second electrode. The system can further comprise a first connector coupled to the first electrode and that applies a negative voltage to the first electrode, and a second connector coupled to the second electrode and that applies a ground voltage to the second electrode, wherein applying the negative voltage to the first electrode and applying the ground voltage to the second electrode comprises negatively biasing the PCM device. The system can further comprise the first connector applying the positive voltage to the first electrode, and the second connector applying a ground voltage to the second electrode, wherein applying the positive voltage to the first electrode and applying the ground voltage to the second electrode comprises positively biasing the PCM device.

公开(公告)号：US20180130885A1

公开(公告)日：2018-05-10

申请号：US15797852

申请日：2017-10-30

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Guy M. Cohen ,  Amlan Majumdar ,  Yu Zhu

IPC: H01L29/205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/205 ,  H01L21/02241 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer, etching the semiconductor layer so as to form a fin and exposing the buffer layer, etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed, and oxidizing the buffer layer and fin so as to form an oxide layer under the fin.