Forward-pass dead instruction identification and removal at run-time
    31.
    发明授权
    Forward-pass dead instruction identification and removal at run-time 失效
    在运行时前进死亡指令识别和删除

    公开(公告)号:US08291196B2

    公开(公告)日:2012-10-16

    申请号:US11323037

    申请日:2005-12-29

    IPC分类号: G06F9/00

    CPC分类号: G06F9/3832 G06F9/3838

    摘要: Apparatuses and methods for dead instruction identification are disclosed. In one embodiment, an apparatus includes an instruction buffer and a dead instruction identifier. The instruction buffer is to store an instruction stream having a single entry point and a single exit point. The dead instruction identifier is to identify dead instructions based on a forward pass through the instruction stream.

    摘要翻译: 公开了用于死指示识别的装置和方法。 在一个实施例中,一种装置包括指令缓冲器和死指令标识符。 指令缓冲器用于存储具有单个入口点和单个出口点的指令流。 死指令标识符是基于通过指令流的向前传递来识别死指令。

    ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION
    34.
    发明申请
    ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION 审中-公开
    启用和禁用分支机构错误预测的第二个执行单位

    公开(公告)号:US20140156977A1

    公开(公告)日:2014-06-05

    申请号:US13994699

    申请日:2011-12-28

    IPC分类号: G06F9/38

    摘要: Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.

    摘要翻译: 描述了在微处理器中启用和/或禁用辅助跳转执行单元(JEU)的技术。 次级JEU被并入微处理器以与主JEU同时操作,并且能够在多个分支上处理同时的分支错误预测。 次级JEU的激活和停用可以由压力计数器或置信计数器来控制。 压力计数器机构增加在处理器内执行的每个分支操作的计数,并在每个周期期间将计数减去衰减值。 置信度计数机制增加每个正确预测分支的计数,并减少每个错误预测的计数。 当计数器超过激活阈值时,每个计数器发出一个激活组件,例如端口绑定硬件组件,开始将微操作绑定到辅助JEU。 计数器机制可能是线程不可知或线程特定的。

    Method and apparatus for speculative execution of uncontended lock instructions
    39.
    发明授权
    Method and apparatus for speculative execution of uncontended lock instructions 有权
    用于推测执行无限制锁定指令的方法和装置

    公开(公告)号:US07529914B2

    公开(公告)日:2009-05-05

    申请号:US10883519

    申请日:2004-06-30

    摘要: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

    摘要翻译: 公开了一种用于在乱序处理器中推测地执行锁定指令的方法和装置。 在一个实施例中,预先确定给定的锁定指令是否将被实际竞争。 如果不是,则锁定指令可以被视为具有可以推测地执行的正常负载微操作。 监视器逻辑可能会查找锁定指令实际上有争议的迹象。 如果没有发现这样的指示,则与锁定指令相对应的投机负载微操作和其他微操作可能会退出。 然而,如果事实上发现这样的指示,则可以重新启动锁定指令,并且可以更新预测机制。